Results 11 to 20 of about 102,564 (236)
Periostin-CCL3 Feedforward Signaling Loop Promotes Cardiac Fibrosis and Cardiomyocyte Necroptosis in Arrhythmogenic Cardiomyopathy. [PDF]
Adv Sci (Weinh)POSTN‐CCL3 signaling forms a feed‐forward circuit between cardiomyocytes and cardiac myofibroblasts in arrhythmogenic cardiomyopathy. POSTN activates JNK/RIP3‐dependent necroptotic signaling and JNK/ETS2‐induced CCL3 expression in cardiomyocytes. In turn, CCL3‐CCR5 signaling in cardiac myofibroblasts activates NF‐κB/p65 and promotes POSTN expression ...
Wu T +12 more
europepmc +2 more sources
A Symbolic Noise Analysis Approach to Word-Length Optimization in DSP Hardware [PDF]
, 2007 This paper addresses the problem of choosing different word-lengths for each functional unit in fixed-point implementations of DSP algorithms. A symbolic-noise analysis method is introduced for high-level synthesis of DSP algorithms in digital hardware ...
Ahmadi, Arash +3 more
core +2 more sources
Genetic algorithm based DSP multiprocessor scheduling [PDF]
, 1996 This paper presents recent work on the application of genetic algorithms to the NP-complete problem of multiprocessor scheduling for audio DSP algorithms.
Amphlett, RW +3 more
core +1 more source
Novel Tone Mapping Method via Macro-Micro Modeling of Human Visual System
IEEE Access, 2019 Tone mapping(TM) aims to adapt high dynamic range (HDR) images to conventional displays with visual information preserved. In this paper, a novel TM method based on macro-micro modeling is proposed, which can address the common problems in existing TM ...
Disheng Miao +4 more
doaj +1 more source
Revista Principia, 2014 Nas últimas décadas a tecnologia tem evoluído rapidamente com a grande demanda por equipamentos para processamento digital de sinais. O Digital Signal Processor (DSP) é um microcontrolador especializado, com alto poder de processamento, utilizado ...
Thamyres T. C. Palitó +4 more
doaj +1 more source
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Ein DSP-Synthesetool für schnelle Low-Power-Implementatierungen von DSP-Algorithmen [PDF]
, 2000 Dieser Artikel präsentiert ein high-level DSP-Synthesetool für Zyklus-limitierte Filter- und Datenpfadapplikationen. Das Synthesetool bildet einen einfachen und schnellen Designweg von der Gleichungsbeschreibung eines DSP-Algorithmus bis hin zu einer ...
Pellandini, Fausto +3 more
core +1 more source
Modeling and Implementation of Space Vector PWM Driver of 3-Phase Induction Motor [PDF]
Engineering and Technology Journal, 2009 This research proposes the design, simulation, and implementation of a three-phase induction motor driver, using voltage-fed Space Vector Pulse Width Modulation technique (SVPWM), which is an advance and modern technique. The SVPWM provides maximum usage
Fadhil Abbas Hassan, Majid K. Al-Khatat
doaj +1 more source
Graphic Library Optimization for MIPS Architecture
Elektronika ir Elektrotechnika, 2020 The aim of this paper and research was to analyse the efficiency of the compiler-generated code for the graphics library and to present results obtained by optimization for the MIPS (Million Instructions Per Second) architecture.
Teodora Novkovic +3 more
doaj +1 more source
Options for DSP code generation
, 2022 S.97-103Advanced Digital Signal Processors (DSP) allow the real-time implementation of more complex algorithms. This results in large programs and in time-consuming development.
Eberlein, E., Herre, J., Grill, B.
core +1 more source