Results 251 to 260 of about 308,092 (299)

ECL fault modelling

IEE Proceedings E Computers and Digital Techniques, 1988
A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the ‘stuck line’ model can be effectively applied to describe circuit failures.
MORANDI, Carlo, L. Niccolai, F. Fantini, S. Gaviraghi   +3 more
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ECL storage elements: modeling of faulty behavior

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1997
Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behavior of two different ECL storage element implementations are examined in the presence of physical faults. While fault models for some implementations of CMOS storage elements have been examined, not much attention has been ...
S.M. Menon, Y.K. Malaiya, A.P. Jayasumana   +2 more
openaire   +1 more source

Accurate delay models for ECL logic synthesis

[1992] Proceedings The European Conference on Design Automation, 2003
The usage of logic synthesis tools for ECL logic has been questionable, among other reasons, because of the discrepancy between the simple, computationally efficient models required by synthesis and the more and more sophisticated models required for accurate simulation. The paper demonstrates that with appropriate choice of modelling parameters, it is
R. Makowitz, A. Wild
openaire   +1 more source

Highly accurate and simple models for CML and ECL gates

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999
In this paper simple and accurate models for the propagation delay of both current mode logic (CML) and emitter-coupled logic (ECL) gates are proposed. The models start from the small signal model properly evaluated. This makes it possible to represent propagation delay with a few terms, providing a better insight into the relationship between delay ...
ALIOTO M, PALUMBO, Gaetano
openaire   +4 more sources

ECLS for the NASA CDG Space Station Model

SAE Technical Paper Series, 1984
<div class="htmlview paragraph">This paper describes the approaches to Environmental Control and Life Support (ECLS) loop closure that have been studied for a permanently manned Space Station, by the NASA Concept Development Group (CDG) and industry.
Ross J. Cushman, Glenn Robinson
openaire   +1 more source

Modeling of faulty behavior of ECL storage elements

Records of the 1993 IEEE International Workshop on Memory Testing, 2002
Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behavior of two different ECL storage element implementations are examined in the presence of physical faults. While fault models for some implementations of CMOS storage elements have been examined, not much attention has been ...
S.M. Menon, Y.K. Malaiya, A.P. Jayasumana   +2 more
openaire   +1 more source

A physical timing model for digital bipolar ECL circuits

1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991
The authors present an accurate physical timing model for large bipolar emitter-coupled-logic (ECL) circuits. A delay model is derived based on device equations and average branch current analysis, and no exhaustive preprocessing or table interpolation is required. The dynamic fanout effects of the ECL circuits can be incorporated by an accurate fanout
A.T. Yang, Y.H. Chang
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Gate level representation of ECL circuits for fault modeling

[1991] Proceedings. First Great Lakes Symposium on VLSI, 2002
Bipolar emitter coupled logic (ECL) devices can now be fabricated at high densities and lower power consumption. With the achievement of low power and high densities, ECL technology is expected to be used widely in high performance digital circuits. This necessitates the need for obtaining optimum gate level models for ECL circuits.
S.M. Menon, A.P. Jayasumana, Y.K. Malaiya   +2 more
openaire   +1 more source

A Fully Analytical Transient Model for an Ecl Inverter Using a Partitioned-Charge-Based BJT Model

1993 Symposium on Semiconductor Modeling and Simulation [Technical Digest], 1994
This paper reports a fully analytical transient model for an ECL inverter using a partitioned-charge-based BJT model. Under the non-quasi-static situation, the fully analytical transient model based on the partitioned charge-based BJT model provides a good explanation of the transient behavior. >
H.J. Huang, J.B. Kuo
openaire   +1 more source

Fault modeling and testable design of 2-level complex ECL gates

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design, 1991
Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model
S.M. Menon, Y.K. Malaiya, A.P. Jayasumana   +2 more
openaire   +1 more source