Results 131 to 140 of about 6,656 (189)

Towards a new vision of PaNET: enhancing reasoning capabilities for better photon and neutron data discovery. [PDF]

J Synchrotron Radiat
Tan T, Bagó B, Busch S, Duyme R, Gaisné G, González Beltrán AN, Görzig H, Koumoutsos G, Krahl R, Millar P, Minotti C, Nentwich M, Schrettner L, Syder K, Rocca-Serra P, Sansone SA, Collins SP.   +16 more
europepmc   +1 more source

R3DMCS: a web server for visualizing structural variation in RNA motifs across experimental 3D structures from the same organism or across species. [PDF]

Bioinformatics
Appasamy SD, Zirbel CL.
europepmc   +1 more source

Runtime Monitoring of Static Fairness Properties

Henzinger TA, Karimi M, Kueffner K, Mallik K.   +3 more
europepmc   +1 more source

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Sequential equivalence checking

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
Summary form only for tutorial. We define sequential equivalence checking (SEC) to be the process of checking functional equivalence between models that do not satisfy the assumption of one-to-one flop mapping. The need for SEC is being driven by the widespread use of system-level modeling in SystemC/C/C++ for developing golden functional reference ...
A. Mathur, M. Fujita, M. Balakrishnan, R. Mitra   +3 more
openaire   +1 more source

Parallel Combinational Equivalence Checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
Combinational equivalence checking (CEC) has been widely applied to ensure design correctness after logic synthesis and technology-dependent optimization in digital integrated circuit design. CEC runtime is often critical for large designs, even when advanced techniques are employed. Three complementary ways for enabling parallelism in CEC are proposed,
Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, Andre I. Reis   +3 more
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Equivalence checking using abstract BDDs

Proceedings International Conference on Computer Design VLSI in Computers and Processors, 2002
We introduce a new equivalence checking method based on abstract BDDs (aBDDs). The basic idea is the following: given an abstraction function, aBDDs reduce the size of BDDs by merging nodes that have the same abstract value. An aBDD has bounded size and can be constructed without constructing the original BDD.
S Jha, Y Lu, M Minea, Clarke, Edmund M
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Checking equivalence for partial implementations

Proceedings of the 38th conference on Design automation - DAC '01, 2001
We consider the problem of checking whether a partial implementation can (still) be extended to a complete design which is equivalent to a given full specification.Several algorithms trading off accuracy and computational resources are presented: Starting with a simple 0,1,&KHarX-based simulation, which allows approximate solutions, but is not able to
C. Scholl, B. Becker
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Equivalence Checking Benchmark

2022
This is the benchmark of Equivalent and Non-equivalent Java/C programs.
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Data-driven equivalence checking

Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications, 2013
We present a data driven algorithm for equivalence checking of two loops. The algorithm infers simulation relations using data from test runs. Once a candidate simulation relation has been obtained, off-the-shelf SMT solvers are used to check whether the simulation relation actually holds.
Rahul Sharma, Eric Schkufza, Berkeley Churchill, Alex Aiken   +3 more
openaire   +1 more source