Results 151 to 160 of about 6,656 (189)

PatEC: Pattern-Based Equivalence Checking

2021
Program parallelization is a common software engineering task, in which parallel design patterns are applied. While the focus of parallelization is on performance, the functional behavior should be kept invariant, i.e., sequential and parallelized program should be functionally equivalent.
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Novel Probabilistic Combinational Equivalence Checking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
Exact approaches to combinational equivalence checking, such as automatic test pattern generation-based, binary decision diagrams (BDD)-based, satisfiability-based, and hybrid approaches, have been proposed over the last two decades. Recently, we proposed another exact approach using signal probability.
null Shih-Chieh Wu, null Chun-Yao Wang, null Yung-Chih Chen   +2 more
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Memory Modeling in ESL-RTL Equivalence Checking

2007 44th ACM/IEEE Design Automation Conference, 2007
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence between ESL arrays and RTL memories can significantly reduce the complexity of a formal equivalence check between the ESL model and the RTL.
Alfred Koelbl, Jerry R. Burch, Carl Pixley   +2 more
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ARDiff: An Equivalence Checking Framework

2020
This repository contains the implementation of ARDiff: an equivalence checking framework that allows scaling symbolic-execution-based equivalence checking for cases that consider two subsequent versions of a program.
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SDL Versus C Equivalence Checking

2005
We present a tool that automatically checks the existence of a bisimulation relation between an SDL specification and the corresponding auto-generated C code. The tool has been used to verify part of the C implementation of a WiFi Medium Access Controller (IEEE 802.11) that has been derived from its original SDL specification using the Telelogic ...
Malek Haroud, Armin Biere
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Parameterized Program Equivalence Checking

2011
In the previous chapter we discussed an approach to verify if two programs are equivalent, thereby proving that the translation (performed by an HLS tool) from high-level design to low-level design is correct. In this chapter, we discuss another approach that guarantees correctness of the translation from high-level design to low-level design, by ...
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RTL-TLM equivalence checking based on simulation

Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08), 2008
The always increasing complexity of digital systems is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at different abstraction levels above RTL. The bottom-up approach is often adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system.
BOMBIERI, Nicola, FUMMI, Franco, PRAVADELLI, Graziano   +2 more
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Semantic program alignment for equivalence checking

Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019
We introduce a robust semantics-driven technique for program equivalence checking. Given two functions we find a trace alignment over a set of concrete executions of both programs and construct a product program particularly amenable to checking equivalence.
Berkeley Churchill, Oded Padon, Rahul Sharma, Alex Aiken   +3 more
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Equivalence Checking of Arithmetic Circuits

2006
Although equivalence checking technology has matured greatly during the last few years and designs with millions of gates can be handled, some specific problems remain to be difficult. Formal verification of arithmetic circuits, especially if multiplication is involved, is one of these problems.
Dominik Stoffel, Evgeny Karibaev, Irina Kufareva, Wolfgang Kunz   +3 more
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Equivalence checking for digital circuits

IEEE Potentials, 2004
Integrated circuit technology has made it possible to produce chips with several millions of transistors. However, the increasingly more complex digital circuit designs and limited time constraints only add to the pressure during the implementation process.
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