Results 31 to 40 of about 131,761 (282)
Fast equivalence-checking for quantum circuits [PDF]
2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010 We perform formal verification of quantum circuits by integrating several techniques specialized to particular classes of circuits. Our verification methodology is based on the new notion of a reversible miter that allows one to leverage existing techniques for simplification of quantum circuits.
Yamashita, Shigeru, Markov, Igor L.
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Fast Validation of Mixed-Signal SoCs
IEEE Open Journal of the Solid-State Circuits Society, 2021 Today’s mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models.
Daniel Stanley +5 more
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Client-specific equivalence checking [PDF]
Proceedings of the 33rd ACM/IEEE International Conference on Automated Software Engineering, 2018 Software is often built by integrating components created by different teams or even different organizations. With little understanding of changes in dependent components, it is challenging to maintain correctness and robustness of the entire system. In this paper, we investigate the effect of component changes on the behavior of their clients.
Federico Mora +3 more
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Towards Symbolic Model-Based Mutation Testing: Combining Reachability and Refinement Checking [PDF]
Electronic Proceedings in Theoretical Computer Science, 2012 Model-based mutation testing uses altered test models to derive test cases that are able to reveal whether a modelled fault has been implemented. This requires conformance checking between the original and the mutated model.
Bernhard K. Aichernig, Elisabeth Jöbstl
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Geometric Model Checking of Continuous Space [PDF]
Logical Methods in Computer Science, 2022 Topological Spatial Model Checking is a recent paradigm where model checking techniques are developed for the topological interpretation of Modal Logic. The Spatial Logic of Closure Spaces, SLCS, extends Modal Logic with reachability connectives that, in
Nick Bezhanishvili +5 more
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Equivalence Checking of Scheduling in High-Level Synthesis Using Deep State Sequences
IEEE Access, 2019 By using high-level synthesis tools, electronic system level design provides a promising solution to fill the growing design productivity gap of high quality hardware systems.
Jian Hu +3 more
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Exact and approximate strategies for symmetry reduction in model checking [PDF]
, 2006 Symmetry reduction techniques can help to combat the state space explosion problem for model checking, but are restricted by the hard problem of determining equivalence of states during search.
Bouquet, Fabrice +2 more
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Finite state automata in the theory of algebraic program schemata
Труды Института системного программирования РАН, 2018 Algebraic models of programs considered in this paper generalize two models of programs introduced by A.A. Lyapunov and A.A. Letichevsky. The theory of these models focuses on the equivalence checking problem for program schemata which are formalization ...
R. I. Podlovchenko
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Effective Marking Equivalence Checking in Systems with Dynamic Process Creation [PDF]
Electronic Proceedings in Theoretical Computer Science, 2013 The starting point of this work is a framework allowing to model systems with dynamic process creation, equipped with a procedure to detect symmetric executions (ie., which differ only by the identities of processes).
Łukasz Fronc
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Strengthening Model Checking Techniques with Inductive Invariants [PDF]
, 2009 This paper describes optimized techniques to efficiently compute and reap benefits from inductive invariants within SAT-based model checking. We address sequential circuit verification, and we consider both equivalences and implications between pairs of ...
Cabodi, Gianpiero +2 more
core +1 more source