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Proceedings of the ACM SIGSOFT 20th International Symposium on the Foundations of Software Engineering, 2012
Before a fault can be fixed, it first must be understood. However, understanding why a system fails is often a difficult and time consuming process. While current automated-debugging techniques provide assistance in knowing where a fault is, developers are left unaided in understanding what a fault is, and why the system is failing. We present Semantic
Nicholas DiGiuseppe, James A. Jones
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Before a fault can be fixed, it first must be understood. However, understanding why a system fails is often a difficult and time consuming process. While current automated-debugging techniques provide assistance in knowing where a fault is, developers are left unaided in understanding what a fault is, and why the system is failing. We present Semantic
Nicholas DiGiuseppe, James A. Jones
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The Journal of the Acoustical Society of America, 1981
An engine diagnostic apparatus includes a first transducer positioned in the oil filler neck of the engine for translating the crankcase pressure waveform into a corresponding electrical waveform having a frequency component proportional to engine speed.
Leonard R. Hulls +2 more
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An engine diagnostic apparatus includes a first transducer positioned in the oil filler neck of the engine for translating the crankcase pressure waveform into a corresponding electrical waveform having a frequency component proportional to engine speed.
Leonard R. Hulls +2 more
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2007 European Control Conference (ECC), 2007
Time has been shown to be determinant in many diagnosis situations. A way to account for time is to enrich the fault signature matrix with time information. However this requires to anticipate the symptoms occurrence order or provide estimates for the symptom occurrence dates.
Louise Trave-Massuyes +1 more
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Time has been shown to be determinant in many diagnosis situations. A way to account for time is to enrich the fault signature matrix with time information. However this requires to anticipate the symptoms occurrence order or provide estimates for the symptom occurrence dates.
Louise Trave-Massuyes +1 more
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1998
Testing fabricated chips for correct temporal behavior is typically done by applying a set of input vector pairs at-speed to the chip under test, and comparing the sampled circuit outputs with their expected logic values. Assuming that the chip is functionally correct, i.e., it produces the correct output values given sufficient time, any discrepancy ...
Mukund Sivaraman, Andrzej J. Strojwas
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Testing fabricated chips for correct temporal behavior is typically done by applying a set of input vector pairs at-speed to the chip under test, and comparing the sampled circuit outputs with their expected logic values. Assuming that the chip is functionally correct, i.e., it produces the correct output values given sufficient time, any discrepancy ...
Mukund Sivaraman, Andrzej J. Strojwas
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1988
A simulation-after-test algorithm for the analog fault diagnosis problem is presented, in which a bound on the maximum number of simultaneous faults is used to minimize the number of test points required. Based on this self-testing algorithm, an analog automatic test program generation (AATPG) for both linear and nonlinear circuits and systems is being
Chin-Long Wey +2 more
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A simulation-after-test algorithm for the analog fault diagnosis problem is presented, in which a bound on the maximum number of simultaneous faults is used to minimize the number of test points required. Based on this self-testing algorithm, an analog automatic test program generation (AATPG) for both linear and nonlinear circuits and systems is being
Chin-Long Wey +2 more
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On Undetectable Faults and Fault Diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010The presence of an undetectable fault ui may modify the response of a detectable fault dj to a test set used for fault diagnosis. This may impact the accuracy of fault diagnosis based on the responses of single faults. Many state-of-the-art diagnosis processes are based on the responses of single stuck-at faults even though their goal is to diagnose ...
Irith Pomeranz, Sudhakar M. Reddy
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Proceedings 15th Symposium on Reliable Distributed Systems, 2002
We consider a dynamic fault diagnosis problem: there are n processors, to be tested in a series of rounds. In every testing round we use a directed matching to have some processors report on the status (good or faulty) of other processors. Also, in each round up to t processors may break down, and we may direct that up to t processors are repaired.
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We consider a dynamic fault diagnosis problem: there are n processors, to be tested in a series of rounds. In every testing round we use a directed matching to have some processors report on the status (good or faulty) of other processors. Also, in each round up to t processors may break down, and we may direct that up to t processors are repaired.
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Fault Diagnosis and Fault Model Aliasing
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit ...
I. Pomeranz, S. Venkataraman, S.M. Reddy
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