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EAGE Conference on Petroleum Geostatistics, 2007
Although faults traditionally have been modelled as membrane-like surfaces, the flow pattern through a fault is affected in a volumetric region. The physical properties of the fault rock will be different from what they were prior to the faulting process.
Skorstad, Arne +4 more
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Although faults traditionally have been modelled as membrane-like surfaces, the flow pattern through a fault is affected in a volumetric region. The physical properties of the fault rock will be different from what they were prior to the faulting process.
Skorstad, Arne +4 more
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Fault Diagnosis and Fault Model Aliasing
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit ...
I. Pomeranz, S. Venkataraman, S.M. Reddy
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Model-Implemented Fault Injection for Hardware Fault Simulation
2010 Workshop on Model-Driven Engineering, Verification, and Validation, 2010This paper presents how model-implemented fault injection can be utilized to simulate the effect of hardware-related faults in embedded systems. A fault injection environment has been developed to enable comparison of experiments at model level and hardware level using Simulink and an Infineon microcontroller, respectively.
Svenningsson R. +3 more
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Fault modeling and fault equivalence in CMOS technology
Journal of Electronic Testing, 1991The need for greater reliability in the fault coverage of test sequences for VLSI circuits has led to the proposal for more accurate fault models and test pattern generation tools. Such improvements bring about a large increase in the fault list to be considered and in the CPU time needed to generate the test.
M.L. Flotted +2 more
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IEE Proceedings E Computers and Digital Techniques, 1988
A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the ‘stuck line’ model can be effectively applied to describe circuit failures.
MORANDI, Carlo +3 more
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A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the ‘stuck line’ model can be effectively applied to describe circuit failures.
MORANDI, Carlo +3 more
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48th Midwest Symposium on Circuits and Systems, 2005., 2005
Testing of digital circuits has traditionally been done using fault models at the gate level or below. Use of these lower level fault models adds complexity and delays testing efforts to later in the design cycle. There is a need to develop a design methodology for performing fault simulation throughout the design process, at many levels of abstraction.
M. Karunaratne +2 more
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Testing of digital circuits has traditionally been done using fault models at the gate level or below. Use of these lower level fault models adds complexity and delays testing efforts to later in the design cycle. There is a need to develop a design methodology for performing fault simulation throughout the design process, at many levels of abstraction.
M. Karunaratne +2 more
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Zero-aliasing for modeled faults
IEEE Transactions on Computers, 1995Summary: When using Built-In Self-Test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division.
Lempel, Mody, Gupta, Sandeep K.
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Generic Fault Modelling for Fault Injection
2011Fault injection is a widely used experimental dependability validation method, with a vast amount of techniques and tools. Within the scope of MOGENTES, an EU 7th framework programme project, tools have been developed which implements three different fault injection techniques; hardware-implemented fault injection, software-implemented fault injection ...
Rickard Svenningsson +3 more
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Model checking fault tolerant systems
Software Testing, Verification and Reliability, 2002AbstractThis paper proposes a modelling approach suitable for formalizing fault tolerant systems, taking into account different fault scenarios. Verification of the properties of such systems is then performed using model checking. A general framework for the formal specification and verification of fault tolerant systems is defined starting from these
BERNARDESCHI, CINZIA +2 more
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Physical Fault Models and Fault Tolerance
2009Dependable systems are obtained by means of extensive testing procedures and the incorporation of fault tolerance mechanisms encompassing error detection (on-line testing) and system recovery. In that context, the characterization of fault models that are both tractable and representative of actual faults constitute an essential basis upon which one ...
Jean Arlat, Yves Crouzet
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