Results 301 to 310 of about 609,388 (352)

A Task-Schedulable Nonvolatile Spintronic Field-Programmable Gate Array

IEEE Magnetics Letters, 2021
Despite the vast hardware resources available in field-programmable gate arrays (FPGAs), the implementation of very large and complex designs on these platforms is a challenging problem. One effective solution is to use task scheduling.
Abdolah Amirany, Kian Jafari, M. H. Moaiyeri   +2 more
semanticscholar   +1 more source

Field-Programmable Gate Arrays

Communications of the ACM, 1999
Field programmable gate arrays (FPGAs) are a flexible alternative to custom integrated circuits. They can implement both combinatorial and sequential logic of tens of thousands of gates. Historically, software has been considered "flexible" with hardware its rigid counterpart in system design.
  +6 more sources

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

International journal of circuit theory and applications, 2018
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in ...
M. Alçin, I. Koyuncu, M. Tuna, M. Varan, I. Pehlivan   +4 more
semanticscholar   +1 more source

Architecture of field-programmable gate arrays [PDF]

Proceedings of the IEEE, 1993
A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity.
Alberto Sangiovanni-Vincentelli, Jonathan Rose, A. El Gamal   +2 more
openaire   +1 more source

Fingerprinting Field Programmable Gate Arrays

2017 IEEE International Conference on Computer Design (ICCD), 2017
The semiconductor industry has adopted a horizontal business model wherein one company designs the Integrated Circuits (ICs), a second company fabricates them and a third one tests and packages them. Separating design from fabrication introduces vulnerabilities in the IC supply chain.
Ashik Poojari, Richard M. Stern, Vinayaka Jyothi, Ramesh Karri   +3 more
openaire   +2 more sources

Note: A high-frequency signal generator based on direct digital synthesizer and field-programmable gate array.

Review of Scientific Instruments, 2017
A high-frequency signal generator based on direct digital synthesizer (DDS) and field-programmable gate array (FPGA) is presented. The FPGA provides the controlling time sequence for the DDS, which has a highest output frequency of 1.4 GHz and a ...
Yuanbo Du, Wenbing Li, Yapeng Ge, Hui Li, K. Deng, Zehuang Lu   +5 more
semanticscholar   +1 more source

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform

IEEE Micro, 2016
This article presents the Zynq UltraScale+ MPSoC (multiprocessor system on chip), which builds on the Zynq-7000 family. Compared to the first-generation Zynq, MPSoC increases performance and power efficiency while significantly improving the integration ...
Sagheer Ahmad, V. Boppana, I. Ganusov, Vinod Kathail, V. Rajagopalan, Ralph Wittig   +5 more
semanticscholar   +1 more source

Parallel placement for field-programmable gate arrays [PDF]

Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03, 2003
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we use the negotiation-based paradigm to parallelize placement. Our new FPGA placer, NAP (Negotiated Analytical Placement), uses an analytical technique for coarse placement and ...
Pak K. Chan, Martine D. F. Schlag
openaire   +1 more source

Design and field programmable gate array implementation of cascade neural network based flux estimator for speed estimation in induction motor drives

, 2017
This study presents design and hardware implementation of cascade neural network (NN) based flux estimator using field programmable gate array (FPGA) for speed estimation in induction motor drives.
A. Venkadesan, S. Himavathi, K. Sedhuraman, A. Muthuramalingam   +3 more
semanticscholar   +1 more source

Antifuse field programmable gate arrays

Proceedings of the IEEE, 1993
An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz.
Jonathan W. Greene, S. Beal, E. Hamdy
openaire   +2 more sources