Results 171 to 180 of about 10,429 (209)

Speed-Sensorless Control of Induction Motor Drives With a STA-FLL Speed Estimation Scheme

IEEE Transactions on Industrial Electronics, 2023
Speed-sensorless control (SSC) techniques enhance the overall reliability while reducing the cost, and thus become attractive in induction motors (IMs).
Huimin Wang, Yongheng Yang, Xinglai Ge   +2 more
exaly   +2 more sources

Standard SOGI-FLL and Its Close Variants: Precise Modeling in LTP Framework and Determining Stability Region/Robustness Metrics [PDF]

IEEE Transactions on Power Electronics, 2021
In recent years, single-phase frequency-locked loops (FLLs) are gaining more popularity as a signal processing and synchronization tool in a wide variety of engineering applications.
Saeed Golestan, Josep M Guerrero, Juan C Vásquez   +2 more
exaly   +2 more sources

New SOGI-FLL Grid Frequency Monitoring with a Finite State Machine Approach for Better Response in the Face of Voltage Sag and Swell Faults [PDF]

Electronics (Switzerland), 2020
The SOGI-FLL (Second-Order Generalized Integrator–Frequency-Locked Loop) is a well-known and simple adaptive filter that allows for estimating the parameters of grid voltage with a small computational burden.
Sajad Abdali Nejad, JOSÉ Matas, Helena Martin   +2 more
exaly   +3 more sources

Some of the next articles are maybe not open access.

Related searches:

An SNR Dependent Model for the CDMA FLL

IEEE Transactions on Signal Processing, 2012
The tracking bandwidth and variance of the code-division multiple-access (CDMA) frequency-lock loop (FLL) are considered in this correspondence. It is shown that the behavior of the discriminator can vary significantly with varying SNRc with corresponding variations in loop performance.
James T. Curran, Gérard Lachapelle, Colin C. Murphy   +2 more
openaire   +1 more source

An Islanding Detection Method by Using Frequency Positive Feedback Based on FLL for Single-Phase Microgrid [PDF]

IEEE Transactions on Smart Grid, 2017
An active islanding detection method based on Frequency-Locked Loop (FLL) for constant power controlled inverter in single-phase microgrid is proposed. This method generates a phase shift comparing the instantaneous frequency obtained from FLL unit with ...
Josep M Guerrero, Juan C Vásquez, Rengang Yang   +2 more
exaly   +2 more sources

Modern Techniques of FLL Tuning

IEEE Transactions on Consumer Electronics, 1982
Over the past few years, tuning systems evolved from manually varying inductances and capacitances to injecting a precise DC voltage to a varactor-controlled tuner.
Farrokh Sutaria, Deepak Vazi ran i
openaire   +1 more source

Modeling and Tuning of Circular Limit Cycle Oscillator FLL With Preloop Filter [PDF]

IEEE Transactions on Industrial Electronics, 2019
Circular limit cycle oscillator-frequency-locked loop (CLO-FLL) is a recently proposed advanced nonlinear technique for the parameter estimation of grid voltage signal. It has fast convergence and can handle dc bias/offset.
Miao Lin Pay, Hafiz Ahmed, Hafiz Ahmed
exaly   +2 more sources

Perception of Influence of FLL on personality

Studia Romanica et Anglica Zagrabiensia, 2008
The argument that language exerts an important influence on the cognitive processes of an individual was first proposed by Edward Sapir, and was also adopted by the sociocultural theory of L. S. Vygotsky and his followers. Lately, the issue of language and identity has become a vibrant topic in SLA research.
Medved Krajnovic, Marta, Juraga, Ivana
openaire   +2 more sources

IEEE 1588 implementation with FLL vs. PLL

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings, 2013
This paper discusses the IEEE 1588 implementation with Frequency Locked Loop (FLL) and Phase Locked Loop (PLL). The work was supported by a Telecom technology provider; the objective is to study the feasibility of IEEE 1588 in the Base Stations (BSs) synchronization, on the basis of minimum structure changes.
openaire   +1 more source

Short locking time FLL and PLL based on a DLL technique

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), 2002
We propose a new circuit technique dedicated to improve the performance of the frequency and phase locked loops (FLLs & PLLs). The presented technique is based on the use of a delay-locked loop (DLL) to improve the speed of the basic architecture of an FLL or a PLL. The DLL is designed to lock on the input reference frequency and its control voltage is
A. Djemouai, M. Sawan, M. Slamani
openaire   +1 more source