Results 51 to 60 of about 70,095 (287)
Journal of Measurement Science and Instrumentation, 2010 Foreground moving object detection is an important process in various computer vision applications such as intelligent visual surveillance,HCI,object-based video compression,etc.One of the most successful moving object detection algorithms is based on ...
Byung-eun LEE +2 more
doaj
SWATI: Synthesizing Wordlengths Automatically Using Testing and Induction [PDF]
, 2013 In this paper, we present an automated technique SWATI: Synthesizing Wordlengths Automatically Using Testing and Induction, which uses a combination of Nelder-Mead optimization based testing, and induction from examples to automatically synthesize ...
Jha, Susmit, Seshia, Sanjit A.
core
The New IEEE-754 Standard for Floating Point Arithmetic [PDF]
, 2008 The current IEEE-754 floating point standard was adopted 23 years ago. IEEE chartered a committee to revise the standard to include new common practice in floating point arithmetic, to incorporate decimal floating point into the standard, and to ...
Markstein, Peter
core +1 more source
Maximum network flow with floating point arithmetic [PDF]
Information Processing Letters, 1998 zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Althaus, E., Mehlhorn, K.
openaire +2 more sources
Evolution of Materials and Device Stacks for HfO2‐Based Ferroelectric Memories
Advanced Materials Interfaces, EarlyView.This review summarizes engineering strategies for HfO2 based ferroelectric memories with focus on FeCAP and FeFET structures. It describes how dopant design, stress effects, and interface engineering improve the bulk ferroelectric response. It further discusses how channel engineering supports reliable memory characteristics and scalable integration ...
Eunjin Kim, Jiyong Woo
wiley +1 more source
ASIC Design of Butterfly Unit Based on Non-Redundant and Redundant Algorithm
Iranian Journal of Electrical and Electronic Engineering, 2021 Fast Fourier Transform (FFT) processors employed with pipeline architecture consist of series of Processing Elements (PE) or Butterfly Units (BU). BU or PE of FFT performs multiplication and addition on complex numbers. This paper proposes a single BU to
P. Kulkarni, B. Hogade, V. Kulkarni
doaj
On Sound Relative Error Bounds for Floating-Point Arithmetic
, 2017 State-of-the-art static analysis tools for verifying finite-precision code compute worst-case absolute error bounds on numerical errors. These are, however, often not a good estimate of accuracy as they do not take into account the magnitude of the ...
baranowski +9 more
core +1 more source
Advanced Materials Interfaces, EarlyView.Atmospheric‐pressure RF plasma deposition enables the fabrication of transparent, superhydrophobic coatings with anti‐reflective functionality. Process optimization yields high optical transmittance, robust environmental stability, and self‐cleaning properties.
Sultan S. Ussenkhan +7 more
wiley +1 more source
PACoGen: A Hardware Posit Arithmetic Core Generator
IEEE Access, 2019 This paper proposes open-source hardware Posit Arithmetic Core Generator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures.
Manish Kumar Jaiswal, Hayden K.-H. So
doaj +1 more source
A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers
IEEE Access, 2020 In this article, we propose an effective algorithm of pipelined dividers for double-precision floating-point numbers. This reduces the latency of the previous pipelined dividers without increasing the lookup table size. The experimental results show that
Juwon Yun +4 more
doaj +1 more source