Results 141 to 150 of about 229,100 (188)

Design of Barker-7 Radar Pulse Compressor Using DSP Architecture Minimization Techniques

International Conference on Communication Systems and Network Technologies
Pulse compression algorithms play an important role in achieving better range resolution (RR) in automobile radar and ultrasonic sensors. The RR is the sensor's capacity to distinguish between two targets positioned in the same angular direction but at ...
Anoopkumar K A, Dayananda B N, Achala G, P. Srihari, Bethi Pardhasaradhi, Linga Reddy Cenkeramaddi   +5 more
semanticscholar   +1 more source

Real-Time Implementation of Coherent Receiver DSP Adopting Stream Split Assignment on GPU for Flexible Optical Access Systems

Journal of Lightwave Technology, 2020
We aim to maximize the flexibility of access networks by combining two trends: digital signal processing (DSP)-based physical (PHY) layer technologies and network function virtualization (NFV). We implement an advanced DSP-PHY on a general-purpose server.
Takahiro Suzuki, Sang-Yuep Kim, J. Kani, J. Terada   +3 more
semanticscholar   +1 more source

A New Hyperchaotic Map Based on Discrete Memristor and Meminductor: Dynamics Analysis, Encryption Application, and DSP Implementation

IEEE transactions on industrial electronics (1982. Print)
At present, discrete memristor is a focus of chaotic mapping. However, the study of discrete memcapacitor and discrete meminductor has not begun. In order to study the dynamics of discrete meminductor and the dynamics of chaotic map containing discrete ...
Xingce Liu, Jun Mou, Yushu Zhang, Yinghong Cao   +3 more
semanticscholar   +1 more source

Folding and Register Minimization Transformation on DSP Filter

IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics Engineering, 2018
This paper presents folding transformation technique on a second order IIR filter or Biquad filter and third order IIR filter. Retiming is done prior to folding transformation. The advantages of folding are reduction in number of arithmetic circuits such
A. Joy, C. Vinitha
semanticscholar   +1 more source

A new class of Hopfield neural network with double memristive synapses and its DSP implementation

The European Physical Journal Plus, 2022
Tengyu Ma, Jun Mou, Huizhen Yan, Yinghong Cao   +3 more
semanticscholar   +1 more source

Design and DSP implementation of a fractional-order detuned laser hyperchaotic circuit with applications in image encryption

Chaos, Solitons & Fractals, 2022
Xuejun Li, Jun Mou, S. Banerjee, Zhisen Wang, Yinghong Cao   +4 more
semanticscholar   +1 more source

Dynamical analysis of the improper fractional-order 2D-SCLMM and its DSP implementation

The European Physical Journal Plus, 2021
Tianming Liu, S. Banerjee, Huizhen Yan, Jun Mou   +3 more
semanticscholar   +1 more source

A fractional-order chaotic system with hidden attractor and self-excited attractor and its DSP implementation

, 2021
Tianming Liu, Huizhen Yan, S. Banerjee, Jun Mou   +3 more
semanticscholar   +1 more source

Design technologies for DSP algorithm implementation on heterogeneous architectures

SPIE Optics + Photonics, 2003
J. McAllister, Y. Yi, Roger Francis Woods, R. Walke, D. Reilly, K. Colgan   +5 more
semanticscholar   +1 more source

High-level algorithm and architecture transformations for DSP synthesis

J. VLSI Signal Process., 1995
K. Parhi
semanticscholar   +1 more source