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Formal verification - is it real enough?
Proceedings. 42nd Design Automation Conference, 2005., 2005While formal verification (FV) of logic designs has been described in an industrial context, it has not yet become a mainstream methodology. The purpose of this report is to summarize a body of experience in the application of industrial-scale FV.
Yaron Wolfsthal, Rebecca M. Gott
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Polynomial Formal Verification of Multipliers
Formal Methods in System Design, 2002zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Martin Keim +4 more
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Formal Verification of Robustness
2015Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor’s characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability.
Niels Thole, Görschwin Fey
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An Improvement in Formal Verification
1995Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usually implemented as a depth-first search of the product state-space of all components in the system, with each (finite state) component modeling the behavior of one ...
Gerard J. Holzmann, Doron A. Peled
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Formal verification of Ada programs
IEEE Transactions on Software Engineering, 1990The Penelope verification editor and its formal basis are described. Penelope is a prototype system for the interactive development and verification of programs that are written in a rich subset of sequential Ada. Because it generates verification conditions incrementally, Penelope can be used to develop a program and its correctness proof in concert ...
David Guaspari +2 more
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18th Annual IEEE Symposium of Logic in Computer Science, 2003. Proceedings., 2003
As designs become more complex, formal verification techniques are becoming increasingly important in the hardware industry. Many different methods are used, ranging from propositional tautology checking up to use of interactive higher-order theorem provers.
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As designs become more complex, formal verification techniques are becoming increasingly important in the hardware industry. Many different methods are used, ranging from propositional tautology checking up to use of interactive higher-order theorem provers.
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Formal Verification Successes at Motorola
Formal Methods in System Design, 2003zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Magdy S. Abadir +4 more
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Formal verification of an optimizing compiler
2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007), 2007Programmers naturally expect that compilers and other code generation tools produce executable code that behaves as prescribed by source programs. However, compilers are complex programs that perform many subtle transformations. Bugs in compilers do happen and can lead to silently producing incorrect executable code from a correct source program.
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