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Formal verification - is it real enough?
Proceedings. 42nd Design Automation Conference, 2005., 2005While formal verification (FV) of logic designs has been described in an industrial context, it has not yet become a mainstream methodology. The purpose of this report is to summarize a body of experience in the application of industrial-scale FV.
Yaron Wolfsthal, Rebecca M. Gott
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Checkers in Formal Verification
2010This chapter continues the description of checkers started in Chap 9. It focuses on the application of checkers to formal verification—composing non-deterministic abstract models. The main feature in checkers supporting non-determinism are free variables, which are introduced in this chapter. We also introduce a special case of free variables: constant
Eduard Cerny +3 more
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Formal Verification of Piece-Wise Linear Feed-Forward Neural Networks
Automated Technology for Verification and Analysis, 2017We present an approach for the verification of feed-forward neural networks in which all nodes have a piece-wise linear activation function. Such networks are often used in deep learning and have been shown to be hard to verify for modern satisfiability ...
Rüdiger Ehlers
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On Games in Formal Verification [PDF]
, 2015 Nel Capitolo 1 facciamo uno studio generale del concetto di "prompt" applicato ai Parity Games. Tale studio permette di raggruppare diverse condizioni di parity, alcune introdotte da noi, altre già presenti in letteratura, sotto un unico framework. Inoltre, in questo capitolo, vengono descritte semplici riduzioni polinomiali da tutte queste condizioni ...
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Formal Verification and Models
2010In this chapter we introduce basic notions of formal verification: the formal verification model and the system clock. We define important classes of properties – safety and liveness – and discuss how formal verification efficiency depends on the property class.
John Havlicek +3 more
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Formal verification of microprocessors
Proceedings of the Fourth Annual Conference on Computer Assurance, 'Systems Integrity, Software Safety and Process Security, 2003A general method is presented for formally verifying the correctness of microprocessor designs. The abstract-level specification of the processor defines the effect of every instruction in terms of a suitably chosen programmer model of the processor.
M. Srivas, M. Bickford
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2011 International Conference on Business Computing and Global Informatization, 2011
Based on the basic concept of the service layer of the requirement meta-modeling frame for network software (RGPS-S), this paper proposed a new formal method to verify its correctness. This paper gives the transform method from BPEL model to Promela model and verifies the model based on SPIN.
Jinzhao Wu, Hao Yang
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Based on the basic concept of the service layer of the requirement meta-modeling frame for network software (RGPS-S), this paper proposed a new formal method to verify its correctness. This paper gives the transform method from BPEL model to Promela model and verifies the model based on SPIN.
Jinzhao Wu, Hao Yang
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Survey of Formal Verification Methods for Smart Contracts on Blockchain
International Conference on New Technologies, Mobility and Security, 2019Due to the immutable nature of distributed ledger technology such as blockchain, it is of utter importance that a smart contract works as intended before employment outside test network.
Yvonne Murray, D. A. Anisi
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Formal Verification Successes at Motorola
Formal Methods in System Design, 2003zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Magdy S. Abadir +4 more
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