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An Improvement in Formal Verification
1995Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usually implemented as a depth-first search of the product state-space of all components in the system, with each (finite state) component modeling the behavior of one ...
Gerard J. Holzmann, Doron Peled
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Formal verification of weakly-hard systems
International Conference on Hybrid Systems: Computation and Control, 2019Weakly-hard systems are real-time systems that can tolerate occasional deadline misses in a bounded manner. Compared with traditional systems with hard deadline constraints, they provide more scheduling flexibility, and thus expand the design space for ...
Chao Huang, Wenchao Li, Qi Zhu
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The Prusti Project: Formal Verification for Rust
NASA Formal Methods, 2022Vytautas Astrauskas +7 more
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Diversity-Driven Automated Formal Verification
International Conference on Software Engineering, 2022E. First, Yuriy Brun
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Formal Verification of Robustness
2015Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor’s characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability.
Görschwin Fey, Niels Thole
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Radiomic features for prostate cancer grade detection through formal verification
La radiologia medica, 2021A. Santone +8 more
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Formal verification of Ada programs
IEEE Transactions on Software Engineering, 1990The Penelope verification editor and its formal basis are described. Penelope is a prototype system for the interactive development and verification of programs that are written in a rich subset of sequential Ada. Because it generates verification conditions incrementally, Penelope can be used to develop a program and its correctness proof in concert ...
David Guaspari +2 more
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18th Annual IEEE Symposium of Logic in Computer Science, 2003. Proceedings., 2003
As designs become more complex, formal verification techniques are becoming increasingly important in the hardware industry. Many different methods are used, ranging from propositional tautology checking up to use of interactive higher-order theorem provers.
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As designs become more complex, formal verification techniques are becoming increasingly important in the hardware industry. Many different methods are used, ranging from propositional tautology checking up to use of interactive higher-order theorem provers.
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Formal Verification in Railways
1999The motive for adopting a formal method is an improved development process with resource savings, a reduced number of errors, and reduced time-to-market. That formal methods potentially can give these benefits is not very controversial since formal methods consider software construction just like construction in any other traditional engineering ...
Arne Borälv, Gunnar Stålmarck
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Formal modeling and verification of microprocessors
IEEE Transactions on Computers, 1995Summary: Formal verification has long been promised as a means of reducing the amount of testing required to ensure correct VLSI devices. Verification requires at least two mathematical models: one that describes the structure of a computer system and another that models its intended behavior. These models are called specifications.
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