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2014, .
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2010
The method of Moore FSM as a Petri network on FPGA is offered. The method is based on the flow-chart transformation to a Petri network with its realization as principal circuit. The features of the Moore FSM circuit realization on FPGA are considered and the method of its synthesis on the base of flow-chart is offered.
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The method of Moore FSM as a Petri network on FPGA is offered. The method is based on the flow-chart transformation to a Petri network with its realization as principal circuit. The features of the Moore FSM circuit realization on FPGA are considered and the method of its synthesis on the base of flow-chart is offered.
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Fourth International ACM Symposium on Field-Programmable Gate Arrays, 1996
This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large ...
Alireza Kaviani, Stephen Brown
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This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large ...
Alireza Kaviani, Stephen Brown
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FPGA-Assisted Deterministic Routing for FPGAs
2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compiletest cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi-CPU platforms. Instead, we propose porting FPGA routing to a CPU+FPGA platform.
Dario Korolija, Mirjana Stojilovic
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2017
Field Programmable Gate Arrays (FPGAs) are currently recognized as the most suitable platform for the implementation of complex digital systems targeting an increasing number of industrial electronics applications. They cover a huge variety of application areas, such as: aerospace, food industry, art, industrial automation, automotive, biomedicine ...
Juan José Rodríguez Andina +2 more
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Field Programmable Gate Arrays (FPGAs) are currently recognized as the most suitable platform for the implementation of complex digital systems targeting an increasing number of industrial electronics applications. They cover a huge variety of application areas, such as: aerospace, food industry, art, industrial automation, automotive, biomedicine ...
Juan José Rodríguez Andina +2 more
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2007 IEEE 15th Signal Processing and Communications Applications, 2007
In this paper, we present the implementation of Direct Sequence Spread Spectrum (DSSS) on Field Programmable Gate Array (FPGA) using one of the hardware definition languages ,Very High Speed Circuit Hardware Description Language (VHDL).AIgorithms are implemented on 3s100 evg100-4 device, belonging to Xlinx FPGA family.These systems are used in mobile ...
Ilker, Ethem Okan +2 more
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In this paper, we present the implementation of Direct Sequence Spread Spectrum (DSSS) on Field Programmable Gate Array (FPGA) using one of the hardware definition languages ,Very High Speed Circuit Hardware Description Language (VHDL).AIgorithms are implemented on 3s100 evg100-4 device, belonging to Xlinx FPGA family.These systems are used in mobile ...
Ilker, Ethem Okan +2 more
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2015Implementation of the scheme of the control device on FPGA for digital devices is suggested. To implement the scheme used by Moore and features automatic basis FPGA, which leads to a decrease in the number of LUT-elements required for the implementation of the scheme.
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A flexible FPGA-to-FPGA communication system
2016 18th International Conference on Advanced Communication Technology (ICACT), 2016In high-performance computing systems, each computing node communicates via a high-speed serial bus to ensure sufficient data transfer bandwidth. However, each computing node of different bus protocols is very difficult to communicate directly, which is not conducive to the extensibility of HPC (High performance computing) clusters.
An Wu, Xi Jin, Xueliang Du, ShuaiZhi Guo
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