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Asynchronously Controlled Frequency Locked Loop
2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2016A frequency-locked loop (FLL) system typically employs synchronous digital counters to estimate the frequency discrepancy between the output of a local oscillator and an external reference clock. We present a novel FIFO-based frequency detector as an alternative to such counters.
Suwen Yang +2 more
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Distributed Frequency-Locked Loops for Wireless Networks
IEEE Transactions on Communications, 2011The establishment of a common frequency reference in a distributed wireless network is a critical factor in enabling any degree of node cooperation in communication and sensing functions. In this paper we introduce Distributed Frequency-Locked Loops (D-FLL's) to control the carrier frequencies of autonomous nodes with wireless communication ...
VARANESE, NICOLA +2 more
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A reconfigurable high-frequency phase-locked loop
Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412), 2004Reconfigurable phase-locked loops (PLLs) present the advantage of fast-frequency acquisition combined with narrow-noise bandwidth, since their parameters can be dynamically adjusted. High-frequency PLLs are generally implemented by means of analog circuits which are not easily reconfigured during operation.
Fernando Rangel de Sousa, Bernard Huyart
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A 50 MHz phase- and frequency-locked loop
IEEE Journal of Solid-State Circuits, 1979A monolithic phase/frequency-locked loop has been developed for operation at up to 50 MHz. The loop combines wide capture range and narrow bandwidth, making it ideal for timing recovery in digital transmission systems. The 24-pin device features an electronically-tuned voltage-controlled LC oscillator and includes the input differentiation and full ...
R. Cordell +3 more
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A Fractional Frequency Synthesizer Using Frequency Locked Loop
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007This paper presents a new architecture for wideband fractional frequency synthesizer. The architecture is based on frequency locked loop (FLL). Fractional division is implemented in this FLL by using two feedback loops which are having different frequency division ratio N and N+1.
A. V. Rejeesh, Pradip Mandal
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Frequency measurement using a frequency locked loop
2011 IEEE Energy Conversion Congress and Exposition, 2011A phase locked loop method is proposed for fast estimation of utility grid frequency, for control and protection purposes in grid-connected power converters. Using a second order generalized integrator (SOGI) and a ‘novel’ frequency locked loop (nFLL), which makes the SOGI frequency adaptive, the proposed SOGI-nFLL detects small and large step changes ...
Zijun Luo +3 more
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Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions [PDF]
IEEE Transactions on Industrial Electronics, 2011 This paper presents a new multiresonant frequencyadaptive synchronization method for grid-connected power converters that allows estimating not only the positive- and negative-sequence components of the power signal at the fundamental frequency but ...
Pedro Rodríguez +2 more
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A digitally-assisted electrothermal frequency-locked loop
2009 Proceedings of ESSCIRC, 2009A digitally-assisted electrothermal frequency-locked loop (FLL) is presented, whose output frequency is determined by the temperature-dependent thermal diffusivity of bulk silicon. In contrast to previous work, its noise bandwidth is defined by a digital, rather than an analog, filter.
S. Mahdi Kashmiri, Kofi A. A. Makinwa
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An alias-locked loop frequency synthesis architecture
2008 IEEE International Symposium on Circuits and Systems, 2008This paper presents a phase-locked loop (PLL) using an aliasing divider, referred to as an alias-locked loop (ALL). The ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider in the feedback path.
Leendert van den Berg, Duncan G. Elliott
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Period Jitter of Frequency-Locked Loops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015This paper presents a spectral analysis of period jitter of frequency-locked loops (FLLs). It is shown that the period jitter of the output clock of the FLL due to stationary noise sources is cyclostationary. It is further shown that the FLL behaves as a time variant loop and there is translation of jitter frequency at the output.
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