Results 201 to 210 of about 54,385 (255)

Frequency and Phase Lock Loop

IEEE Transactions on Consumer Electronics, 1977
A new electronic subsystem has been developed: The frequency and phase lock loop. It has an extended acquisition range compared to the standard phase lock loop. It will be advantageous to use this new loop in all applications where a simultaneous need for large acquisition range and a narrow tracking bandwidth can justify the added complexity of the ...
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Frequency Response of Phase Locked Loops

IEEE Transactions on Broadcast and Television Receivers, 1971
This paper is concerned with the design of the phase locked loop (PLL) to be used as an FM demodulator. With the introduction of the PLL IC and the trend of designing inductorless circuits, there has been much interest in the PLL FM demodulator.1'2 The discussion in this paper concentrates on the steady state response of the PLL to sinusoidally ...
Richard Bernstein, Andreg. Vacroux
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Phase-Locked Loop Frequency Synthesizers

1998
The indirect or phase-locked loop frequency synthesizer offers the distinct advantage over other types of synthesizers of possible low-cost IC integration. This is the main reason why almost all mobile communication chip sets use this circuit. But of course there are also some disadvantages, which require careful study and proper design. Two main areas
J. Craninckx, M. Steyaert
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Phase-Lock Loop Frequency Acquisition Study

IRE Transactions on Space Electronics and Telemetry, 1962
The ability of a phase-lock loop using a proportional plus integral control filter to acquire a noisy signal when the local oscillator is being swept was determined empirically by means of a low-frequency, GEESE1 model of such a system. The effects of the damping factor and natural frequency on the frequency acquisition properties of linear loops (as ...
J. P. Frazier, J. Page
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Fractional phase-locked loop frequency synthesizer

SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720), 2004
The fractional frequency synthesizer is similar to the divide-by-N phase-locked loop (PLL) (divider in feedback path). However, the output frequency of the voltage-controlled oscillator (VCO) is not restricted to integral multiples of the reference signal only.
M. Stork, P. Kaspar
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Design of delay-locked loop for wide frequency locking range

2013 International SoC Design Conference (ISOCC), 2013
In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit’s bias current is keep at lower level.
Hsun-Hsiang Chen, Zih-Hsiang Wong, Shen-Li Chen   +2 more
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Modeling Multipath Effects on Frequency Locked Loops

The International Technical Meeting of the The Institute of Navigation, 2020
This paper investigates the impact of non-line-of-site (NLOS) and multipath signals on frequency-locked loops (FLLs), which are commonly used to obtain Doppler shift measurements for velocity estimation in radio navigation. First, we use theory to model the effects of NLOS signals on the Doppler estimate produced by a conventional FLL with an ...
Liangchun Xu, Jason Rife
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Radio Frequency Design of Fast Locking Digital Phase Locked Loop

2015 International Conference on Computing Communication Control and Automation, 2015
Phase locked loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a reference signal. The performance of PLL is primarily dependent on the lock time, it is the time the PLL takes to adapt and settle after a sudden change of the input signal frequency.
Akshay Dalal, Neha Digrase, Rahul Lanjewar   +2 more
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Stability of Frequency Locked Loops

1989
Passive frequency standards are characterized by the use of a reference resonance to stabilize the frequency of an external probe oscillator. A common configuration is shown in Fig. 1 [1–6]. The probe oscillator generally has phase modulation imposed on the carrier in order to interrogate the resonance with a minimum of offset.
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Period Jitter of Frequency-Locked Loops

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015
This paper presents a spectral analysis of period jitter of frequency-locked loops (FLLs). It is shown that the period jitter of the output clock of the FLL due to stationary noise sources is cyclostationary. It is further shown that the FLL behaves as a time variant loop and there is translation of jitter frequency at the output.
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