Results 211 to 220 of about 54,385 (255)
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Frequency synthesis using pulse width locked loop
2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2009Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for δΣ Modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed
D.Y. Aksin, P.B. Basyurt, H.U. Uyanik
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Interference in Frequency-Locked Doppler Tracking Loops
IEEE Transactions on Aerospace and Electronic Systems, 1984The effects of interference on frequency-locked Doppler tracking loops are investigated. Conditions for jump from locking on the desired signal to locking on the interfering signal are established. Parasitic frequency modulation of the desired signal results when the other signal interferes with it.
Y. Bar-Ness, H. Bunin
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Phase-Locked Loop Pull-In Frequency
IEEE Transactions on Communications, 1974A computerized procedure for obtaining the pull-in frequency of a phase-locked loop is described. The procedure, which consists of solving for the limit cycle of the out-of-lock loop and finding the frequency offset below which no solution exists, is quite general with respect to phase detector function and loop filter.
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CMOS phase-locked loops for frequency synthesis
2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010As wireless communication systems evolve toward higher frequencies, higher bandwidths, and multi-standard capabilities, the performance of their phase-locked loops (PLLs) becomes increasingly critical to overall system performance. Additionally, PLLs often must be integrated with large digital blocks, so there is strong and increasing economic pressure
Ian Galton +3 more
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Phase-Locked Loop based frequency adder
Signal Processing, 1986Abstract The Phase-Locked Loop (PLL) frequency adder is based on the fractional N technique which is successfully applied in the frequency synthesis field. This method may be used to add two frequencies / tf 1 and / tf 2 , i.e., to give a one frequency equal to / tf 1 + / tf 2 .
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Pulsed phase-locked loop calibration over frequency
IEEE Transactions on Instrumentation and Measurement, 1996This paper presents a method of correcting for unwanted phase shifts introduced by interchanging ultrasonic transducers and other measurement system components when using the pulsed phase-locked loop (PPLL) ultrasonic system. Theory is derived mathematically separating phase errors into their constituents.
M.E. Froggatt, S.G. Allison, J.P. Moore
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Design of high frequency phase locked loop
2010 INTERNATIONAL CONFERENCE ON COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES, 2010A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs.
Raman Bondare +3 more
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An alias-locked loop frequency synthesis architecture
2008 IEEE International Symposium on Circuits and Systems, 2008This paper presents a phase-locked loop (PLL) using an aliasing divider, referred to as an alias-locked loop (ALL). The ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider in the feedback path.
Leendert van den Berg, Duncan G. Elliott
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A digitally-assisted electrothermal frequency-locked loop
2009 Proceedings of ESSCIRC, 2009A digitally-assisted electrothermal frequency-locked loop (FLL) is presented, whose output frequency is determined by the temperature-dependent thermal diffusivity of bulk silicon. In contrast to previous work, its noise bandwidth is defined by a digital, rather than an analog, filter.
S.M. Kashmiri, K.A.A. Makinwa
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Multi-frequency zero-jitter delay-locked loop
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 2002The use of an all-digital phase locked loop (ADPLL) approach in a delay-locked loop circuit is described. This design is applied to a system with two processing units, a master central processing unit (CPU) and a slave system chip, that share the same bus.
A. Efendovich +3 more
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