Results 121 to 130 of about 4,819 (258)

On the Design of a Class of Analog Filters Whose Impulse Response Is a Mittag‐Leffler Function

open access: yesInternational Journal of Circuit Theory and Applications, EarlyView.
Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known forms are summarized in this work. Simulation results using Cadence and experimental results using an FPAA validate the introduced concept. ABSTRACT Fractional‐order filters whose impulse response is a Mittag‐Leffler (M‐L) function in any of its known
Julia Nako   +3 more
wiley   +1 more source

A Co‐Designed Implicit‐Reset Path PFD and Current Mismatch Compensated CP Enabling Sub‐0.5% Mismatch and Dead Zone‐Free for Low‐Spur PLLs

open access: yesInternational Journal of Circuit Theory and Applications, EarlyView.
A co‐designed implicit‐reset phase‐frequency detector (PFD) and nonlinear amplifier‐assisted charge pump (CP) achieve dead zone‐free operation from 10 MHz to 4.7 GHz with < 0.5% current mismatch without calibration, enabling −80 dBc of reference spur and 0.50 ps of RMS jitter in a 180 nm of CMOS PLL.
A. Ghaemnia   +3 more
wiley   +1 more source

Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization

open access: yesInternational Journal of Circuit Theory and Applications, EarlyView.
This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley   +1 more source

Parallel Multi‐Operand Addition Using CPA‐Trees and Carry‐Select Adders

open access: yesInternational Journal of Circuit Theory and Applications, EarlyView.
A balanced parallel CPA‐tree architecture with CSLA reduces the critical‐path delay of multi‐operand addition while preserving structural regularity. ASIC results demonstrate delay reductions of up to 34% with low area overhead, providing an efficient and scalable solution for high‐performance arithmetic.
Lucas R. Kieslich   +3 more
wiley   +1 more source

An Ultra‐Low‐Power Biopotential Acquisition Analog Front‐End Chip for Wearable Devices

open access: yesInternational Journal of Circuit Theory and Applications, EarlyView.
A 0.8‐V, 1.2‐μW biopotential AFE combines a chopper‐stabilized CCIA with dual‐time‐scale EDO management. The slow DSL preserves > 1 GΩ input impedance, whereas an event‐triggered fast‐recovery path shortens return to the linear range after abrupt electrode‐offset disturbances. ABSTRACT A 0.8‐V, 1.2‐μW biopotential analog front‐end (AFE) IC is presented
Zhang Xin   +4 more
wiley   +1 more source

Laser‐Textured Field‐Engineered Interface for Robust Dry‐Processed Cathodes in Lithium‐Ion Batteries

open access: yesENERGY &ENVIRONMENTAL MATERIALS, EarlyView.
Laser‐patterned dry electrodes applied to current collectors could serve as a promising alternative to the limitations of conventional dry electrodes. Laser technology provides a fast and simple method to enhance the surface roughness of current collectors, improving the adhesion at the electrode–current collector interface.
Chaerin Jung   +8 more
wiley   +1 more source

Home - About - Disclaimer - Privacy