Results 151 to 160 of about 260,743 (188)

VIRI: a visualization tool for tree reconciliations. [PDF]

open access: yesBMC Bioinformatics
Patrignani M   +3 more
europepmc   +1 more source

Constrained Graph Layout

Constraints, 1997
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
He, Weiqing, Marriott, Kim
openaire   +2 more sources

Linear layouts of weakly triangulated graphs

Discrete Mathematics, Algorithms and Applications, 2014
A graph [Formula: see text] is said to be triangulated if it has no chordless cycles of length 4 or more. Such a graph is said to be rigid if, for a valid assignment of edge lengths, it has a unique linear layout and non-rigid otherwise. Damaschke [Point placement on the line by distance data, Discrete Appl. Math.
Mukhopadhyay, Asish   +3 more
openaire   +1 more source

Linear Layout of Directed Grid Graph

Mathematics in Computer Science, 2015
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Rajasingh, Indra   +3 more
openaire   +1 more source

Graph Layout Using Queues

2013
We study the problem of laying out the edges of a graph using queues. In a k queue layout, vertices of the graph are placed in some linear order and each edge is assigned to exactly one of the k queues so that the edges assigned to each queue obey a first-in/first-out discipline.
Heath, Lenwood S., Rosenberg, Arnold L.
openaire   +2 more sources

A Maxent-Stress Model for Graph Layout

IEEE Transactions on Visualization and Computer Graphics, 2012
In some applications of graph visualization, input edges have associated target lengths. Dealing with these lengths is a challenge, especially for large graphs. Stress models are often employed in this situation. However, the traditional full stress model is not scalable due to its reliance on an initial all-pairs shortest path calculation. A number of
Emden R, Gansner   +2 more
openaire   +2 more sources

Area-efficient graph layouts

21st Annual Symposium on Foundations of Computer Science (sfcs 1980), 1980
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph.
openaire   +1 more source

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