Results 331 to 340 of about 1,421,171 (369)
Some of the next articles are maybe not open access.
Scalable Force Directed Graph Layout Algorithms Using Fast Multipole Methods
International Symposium on Parallel and Distributed Computing, 2012We present an extension to ExaFMM, a Fast Multipole Method library, as a generalized approach for fast and scalable execution of the Force-Directed Graph Layout algorithm.
E. Yunis, Rio Yokota, A. Ahmadia
semanticscholar +1 more source
Intelligent design of shear wall layout based on graph neural networks
Advanced Engineering Informatics, 2023Pengju Zhao +3 more
semanticscholar +1 more source
2013
We study the problem of laying out the edges of a graph using queues. In a k queue layout, vertices of the graph are placed in some linear order and each edge is assigned to exactly one of the k queues so that the edges assigned to each queue obey a first-in/first-out discipline.
Heath, Lenwood S., Rosenberg, Arnold L.
openaire +2 more sources
We study the problem of laying out the edges of a graph using queues. In a k queue layout, vertices of the graph are placed in some linear order and each edge is assigned to exactly one of the k queues so that the edges assigned to each queue obey a first-in/first-out discipline.
Heath, Lenwood S., Rosenberg, Arnold L.
openaire +2 more sources
Automated building layout generation using deep learning and graph algorithms
Automation in Construction, 2023Lufeng Wang +6 more
semanticscholar +1 more source
21st Annual Symposium on Foundations of Computer Science (sfcs 1980), 1980
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph.
openaire +1 more source
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph.
openaire +1 more source
InstructScene: Instruction-Driven 3D Indoor Scene Synthesis with Semantic Graph Prior
International Conference on Learning RepresentationsComprehending natural language instructions is a charming property for 3D indoor scene synthesis systems. Existing methods directly model object joint distributions and express object relations implicitly within a scene, thereby hindering the ...
Chenguo Lin, Yadong Mu
semanticscholar +1 more source
Proc. ACM Manag. Data
High-dimensional vector similarity search (HVSS) is gaining prominence as a powerful tool for various data science and AI applications. As vector data scales up, in-memory indexes pose a significant challenge due to the substantial increase in main ...
Mengzhao Wang +9 more
semanticscholar +1 more source
High-dimensional vector similarity search (HVSS) is gaining prominence as a powerful tool for various data science and AI applications. As vector data scales up, in-memory indexes pose a significant challenge due to the substantial increase in main ...
Mengzhao Wang +9 more
semanticscholar +1 more source
EchoScene: Indoor Scene Generation via Information Echo over Scene Graph Diffusion
European Conference on Computer VisionWe present EchoScene, an interactive and controllable generative model that generates 3D indoor scenes on scene graphs. EchoScene leverages a dual-branch diffusion model that dynamically adapts to scene graphs.
Guangyao Zhai +7 more
semanticscholar +1 more source
The Effect of Graph Layout on the Perception of Graph Properties
Eurographics Conference on Visualization, 2020Elektra Kypridemou +2 more
semanticscholar +1 more source