Results 231 to 240 of about 77,762 (283)
RandMScan: accelerating parallel scan via matrix computation and random-jump strategy. [PDF]
Sci RepPeng S, Lin X, Zhang Y, Xiao Y, Hu Y.
europepmc +1 more source
Research on electromagnetic compatibility analysis of automation equipment based on generative adversarial networks and pulse sparse convolution. [PDF]
PLoS OneDing W, Feng D.
europepmc +1 more source
Single photon event-driven 3D imaging. [PDF]
Commun EngVicente Sola A +3 more
europepmc +1 more source
HE-BiDet: A Hardware Efficient Binary Neural Network Accelerator for Object Detection in SAR Images. [PDF]
Micromachines (Basel)Zhang D +5 more
europepmc +1 more source
Some of the next articles are maybe not open access.
Related searches:
Related searches:
Hardware Accelerated Voxelisation
Computers & Graphics, 2000Abstract This paper presents a hardware accelerated approach to the voxelization of a wide range of 3D objects, including curves/surfaces, solids, and volumetric CSG models. It allows 3D scenes to be modeled and manipulated in their own representations, and generates the volume representations of regions of interest on-the-fly for volumetric ...
Shiaofen Fang, Hongsheng Chen
openaire +1 more source
Hardware Accelerated Data Analysis
Parallel Computing in Electrical Engineering, International Conference on, 2004In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times.
Franzmeier, M. +4 more
openaire +1 more source
Multimedia Execution Hardware Accelerator
Journal of VLSI signal processing systems for signal, image and video technology, 2001zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Hakkennes, Edwin, Vassiliadis, Stamatis
openaire +2 more sources
Hybrid binary-unary hardware accelerator
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019Stream-based computing such as stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the area saving comes at an exponential price in latency, making the area × delay cost unattractive.
S. Rasoul Faraji, Kia Bazargan
openaire +1 more source
IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology', 2003
A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit.
openaire +1 more source
A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit.
openaire +1 more source
2006 International Conference on Field Programmable Logic and Applications, 2006
Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system.
Michael Gilroy, James Irvine
openaire +1 more source
Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system.
Michael Gilroy, James Irvine
openaire +1 more source