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Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023Number theoretic transform (NTT) is useful for the acceleration of polynomial multiplication, which is the main performance bottleneck in the next-generation cryptographic schemes.
Jianan Mu +10 more
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High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator
IEEE Transactions on Emerging Topics in Computing, 2023The convolutional neural network (CNN) is a significant part of the artificial intelligence (AI) systems widely used in different tasks. The binarized neural networks (BNNs) reduce power consumption and hardware overhead to answer the demands for using ...
Milad Tanavardi Nasab +3 more
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Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2023The looming threat of an adversary with quantum computing capability led to a worldwide research effort towards identifying and standardizing novel post-quantum cryptographic primitives.
Naina Gupta +3 more
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FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio
IEEE Transactions on Neural Networks and Learning Systems, 2021The field-programmable gate array (FPGA)-based CNN hardware accelerator adopting single-computing-engine (CE) architecture or multi-CE architecture has attracted great attention in recent years.
Wenjin Huang +6 more
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A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme
Design, Automation and Test in Europe, 2021Polynomial multiplication is one of the most time-consuming operations utilized in lattice-based post-quantum cryptography (PQC) schemes. CRYSTALS-KYBER is a lattice-based key encapsulation mechanism (KEM) and it was recently announced as one of the four
Ferhat Yaman +3 more
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BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
IEEE Journal of Solid-State Circuits, 2022We introduce an area/energy-efficient precision-scalable neural network accelerator architecture. Previous precision-scalable hardware accelerators have limitations such as the under-utilization of multipliers for low bit-width operations and the large ...
Sungju Ryu +6 more
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CoHA-NTT: A Configurable Hardware Accelerator for NTT-based Polynomial Multiplication
IACR Cryptology ePrint Archive, 2022—In this paper, we introduce a configurable hardware architecture that can be used to generate unified and parametric NTT-based polynomial multipliers that support a wide range of parameters of lattice-based cryptographic schemes proposed for post-quantum ...
Kemal Derya +3 more
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Hardware Accelerated Voxelisation
Computers & Graphics, 2000Abstract This paper presents a hardware accelerated approach to the voxelization of a wide range of 3D objects, including curves/surfaces, solids, and volumetric CSG models. It allows 3D scenes to be modeled and manipulated in their own representations, and generates the volume representations of regions of interest on-the-fly for volumetric ...
Shiaofen Fang, Hongsheng Chen
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An Efficient Hardware Accelerator for Sparse Transformer Neural Networks
International Symposium on Circuits and Systems, 2022Transformers have been an indispensable staple in deep learning. However, it is challenging to realize efficient deployment for Transformer-based model due to their substantial computation and memory demands.
Chao Fang +6 more
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Hardware Accelerated Data Analysis
Parallel Computing in Electrical Engineering, International Conference on, 2004In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times.
Franzmeier, M. +4 more
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