Results 271 to 280 of about 1,050,120 (328)

Multimedia Execution Hardware Accelerator

Journal of VLSI signal processing systems for signal, image and video technology, 2001
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Hakkennes, Edwin, Vassiliadis, Stamatis
openaire   +2 more sources

High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator

2022 30th International Conference on Electrical Engineering (ICEE), 2022
Neural networks have shown a high ability to model and solve complex problems. Hardware implementation of the neural network can also increase the efficiency of this system and, in particular neural network hardware accelerators.
Milad Tanavardi Nasab, Arefe Amirany, M. H. Moaiyeri, Kian Jafari   +3 more
semanticscholar   +1 more source

Hybrid binary-unary hardware accelerator

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Stream-based computing such as stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the area saving comes at an exponential price in latency, making the area × delay cost unattractive.
S. Rasoul Faraji, Kia Bazargan
openaire   +1 more source

An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA

IEEE Embedded Systems Letters
Field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed.
Xiaodi Yin, Zhipeng Wu, Dejian Li, Chongfei Shen, Yu Liu   +4 more
semanticscholar   +1 more source

A High-Performance Pixel-Level Fully Pipelined Hardware Accelerator for Neural Networks

IEEE Transactions on Neural Networks and Learning Systems
The design of convolutional neural network (CNN) hardware accelerators based on a single computing engine (CE) architecture or multi-CE architecture has received widespread attention in recent years.
Zhan Li, Zhihan Zhang, Jie Hu, Qunkang Meng, Xingyu Shi, Jun Luo, Hao Wang, Qijun Huang, Sheng Chang   +8 more
semanticscholar   +1 more source

FFT hardware accelerator

IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology', 2003
A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit.
openaire   +1 more source

RAID 6 Hardware Acceleration

2006 International Conference on Field Programmable Logic and Applications, 2006
Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system.
Michael Gilroy, James Irvine
openaire   +1 more source

Hardware accelerated multichannel receiver

2009 IEEE Aerospace conference, 2009
Software-based radios implemented on general-purpose processors are cheaper, easier, and faster to develop, maintain, and upgrade than hardware-based equivalents. Unfortunately, today's general-purpose processors are not fast enough to process certain waveforms. The current alternative is to use application-specific integrated circuits (ASICs) or field-
Eric J. McDonald, Nathaniel W. Schlossberg, Eugene Grayver   +2 more
openaire   +1 more source

GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing

Micro, 2020
Graph processing workloads are memory intensive with irregular access patterns and large memory footprint resulting in low data locality. Their popular software implementations typically employ either Push or Pull style propagation of changes through the
Shafiur Rahman, N. Abu-Ghazaleh, Rajiv Gupta   +2 more
semanticscholar   +1 more source

$\pi$π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations

IEEE transactions on computers, 2020
Bundle adjustment (BA) is a fundamental optimization technique used in many crucial applications, including 3D scene reconstruction, robotic localization, camera calibration, autonomous driving, street view map generation, and even space exploration etc.
Qiang Liu, S. Qin, Bo Yu, Jie Tang, Shaoshan Liu   +4 more
semanticscholar   +1 more source