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Hardware Acceleration of Neural Graphics [PDF]

International Symposium on Computer Architecture, 2023
Rendering and inverse rendering techniques have recently attained powerful new capabilities and building blocks in the form of neural representations (NR), with derived rendering techniques quickly becoming indispensable tools next to classic computer ...
Muhammad Husnain Mubarik, R. Kanungo, Tobias Zirr, Rakesh Kumar   +3 more
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TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings [PDF]

International Symposium on Computer Architecture, 2023
In response to innovations in machine learning (ML) models, production workloads changed radically and rapidly. TPU v4 is the fifth Google domain specific architecture (DSA) and its third supercomputer for such ML models. Optical circuit switches (OCSes)
N. Jouppi, George Kurian, Sheng Li, Peter C. Ma, R. Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, C. Young, Xiaoping Zhou, Zongwei Zhou, David A. Patterson   +13 more
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Gen-NeRF: Efficient and Generalizable Neural Radiance Fields via Algorithm-Hardware Co-Design [PDF]

International Symposium on Computer Architecture, 2023
Novel view synthesis is an essential functionality for enabling immersive experiences in various Augmented- and Virtual-Reality (AR/VR) applications, for which Neural Radiance Field (NeRF) has emerged as the state-of-the-art (SOTA) technique.
Y. Fu, Zhifan Ye, Jiayi Yuan, Shunyao Zhang, Sixu Li, Haoran You, Yingyan Lin   +6 more
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Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models

ACM Transactions on Architecture and Code Optimization (TACO), 2023
Deep learning (DL) models such as convolutional neural networks (ConvNets) are being deployed to solve various computer vision and natural language processing tasks at the edge.
Hadjer Benmeziane, Hamza Ouarnoughi, K. El Maghraoui, S. Niar   +3 more
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OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization [PDF]

International Symposium on Computer Architecture, 2023
Transformer-based large language models (LLMs) have achieved great success with the growing model size. LLMs' size grows by 240× every two years, which outpaces the hardware progress and makes model inference increasingly costly.
Cong Guo, Jiaming Tang, Weiming Hu, Jingwen Leng, Chen Zhang, Fan Yang, Yun-Bo Liu, Minyi Guo, Yuhao Zhu   +8 more
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ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification

International Symposium on Computer Architecture, 2023
With the rapid growth of classification scale in deep learning systems, the final classification layer becomes extreme classification with a memory footprint exceeding the main memory capacity of the CPU or GPU.
Siqi Li, Fengbin Tu, Liu Liu, Jilan Lin, Zheng Wang, Yangwook Kang, Yufei Ding, Yuan Xie   +7 more
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ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks [PDF]

ACM Transactions on Architecture and Code Optimization (TACO), 2023
‘‘Extreme edge”1 devices, such as smart sensors, are a uniquely challenging environment for the deployment of machine learning. The tiny energy budgets of these devices lie beyond what is feasible for conventional deep neural networks, particularly in ...
Zachary Susskind, Aman Arora, Igor D. S. Miranda, Alan T. L. Bacellar, L. A. Q. Villon, R. Katopodis, Leandro S. de Araújo, D. Dutra, P. M. V. Lima, F. M. G. França, Mauricio Breternitz Jr., L. John   +11 more
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Software-Hardware Co-Optimization for Computational Chemistry on Superconducting Quantum Processors [PDF]

International Symposium on Computer Architecture, 2021
Computational chemistry is the leading application to demonstrate the advantage of quantum computing in the near term. However, large-scale simulation of chemical systems on quantum computers is currently hindered due to a mismatch between the ...
Gushu Li, Yunong Shi, Ali Javadi-Abhari
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HeapCheck: Low-cost Hardware Support for Memory Safety

ACM Transactions on Architecture and Code Optimization (TACO), 2022
Programs written in C/C++ are vulnerable to memory-safety errors like buffer-overflows and use-after-free. While several mechanisms to detect such errors have been previously proposed, they suffer from a variety of drawbacks, including poor performance ...
Gururaj Saileshwar, R. Boivie, Tong Chen, Benjamin Segal, A. Buyuktosunoglu   +4 more
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HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformers [PDF]

International Symposium on High-Performance Computer Architecture, 2022
While vision transformers (ViTs) have continuously achieved new milestones in the field of computer vision, their sophisticated network architectures with high computation and memory costs have impeded their deployment on resource-limited edge devices ...
Peiyan Dong, Mengshu Sun, Alec Lu, Yanyue Xie, Li-Yu Daisy Liu, Zhenglun Kong, Xin Meng, Z. Li, Xue Lin, Zhenman Fang, Yanzhi Wang   +10 more
semanticscholar   +1 more source