Results 31 to 40 of about 126,905 (80)
CraterLake: a hardware accelerator for efficient unbounded computation on encrypted data
International Symposium on Computer Architecture, 2022 Nikola Samardzic +8 more
semanticscholar +1 more source
, 2021 The number and diversity of consumer devices are growing rapidly, alongside their target applications' memory consumption. Unfortunately, DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices.
Boroumand, Amirali +10 more
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WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow
, 2023 With the cross-fertilization of applications and the ever-increasing scale of models, the efficiency and productivity of hardware computing architectures have become inadequate.
Gu, Jiangyuan +6 more
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TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems
, 2023 Processing-in-memory (PIM) promises to alleviate the data movement bottleneck in modern computing systems. However, current real-world PIM systems have the inherent disadvantage that their hardware is more constrained than in conventional processors (CPU,
Guo, Yuxin +5 more
core
, 2010 Dans le but de satisfaire les différentes contraintes matérielles, une exploration architecturale peut permettre de définir les paramètres optimaux d'un processeur VLIW (Very Long Instruction Word) pour une application donnée tels que le nombre d'unités ...
Yviquel, Hervé
core
Processing-using-DRAM (PUD) architectures impose a restrictive data layout and alignment for their operands, where source and destination operands (i) must reside in the same DRAM subarray (i.e., a group of DRAM rows sharing the same row buffer and row ...
Esposito, Emanuele G. +3 more
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A Prior Study of Split Compilation and Approximate Floating-Point Computations
, 2011 From a future perspective of heterogeneous multicore processors, we studied several optimization processes specified for floating-point numbers in this internship.
Taguchi, Takanoki
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Evolutionary Large Language Models for Hardware Security: A Comparative Survey
Automating hardware (HW) security vulnerability detection and mitigation during the design phase is imperative for two reasons: (i) It must be before chip fabrication, as post-fabrication fixes can be costly or even impractical; (ii) The size and ...
Akyash, Mohammad, Kamali, Hadi Mardani
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We experimentally analyze the computational capability of commercial off-the-shelf (COTS) DRAM chips and the robustness of these capabilities under various timing delays between DRAM commands, data patterns, temperature, and voltage levels.
Bostanci, F. Nisa +10 more
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GraphGPT: Graph Instruction Tuning for Large Language Models
Graph Neural Networks (GNNs) have evolved to understand graph structures through recursive exchanges and aggregations among nodes. To enhance robustness, self-supervised learning (SSL) has become a vital tool for data augmentation.
Cheng, Suqi +7 more
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