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FactorFlow: Mapping GEMMs on Spatial Architectures through Adaptive Programming and Greedy Optimization [PDF]

Ronzani, Marco, Silvano, Cristina
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Reinhardt: Real-time Reconfigurable Hardware Architecture for Regular Expression Matching in DPI

Asia-Pacific Computer Systems Architecture Conference, 2021
Regular expression (regex) matching is an integral part of deep packet inspection (DPI) but a major bottleneck due to its low performance. For regex matching (REM) acceleration, FPGA-based studies have emerged and exploited parallelism by matching ...
Taejune Park, Jaehyun Nam, S. Na, Jaewoong Chung, Seungwon Shin   +4 more
semanticscholar   +1 more source

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

International Symposium on Computer Architecture, 2021
Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory ...
Sukhan Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seung-young Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, N. Kim   +15 more
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HERMES: Hardware-Efficient Speculative Dataflow Architecture for Bonsai Merkle Tree-Based Memory Authentication

IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Emerging byte-addressable Non-Volatile Memory (NVM) technology, although promising superior memory density and ultra-low energy consumption, poses unique challenges to guaranteeing memory confidentiality, integrity, and crash-consistency.
Yu Zou, Amro Awad, Mingjie Lin
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A Bus Authentication and Anti-Probing Architecture Extending Hardware Trusted Computing Base Off CPU Chips and Beyond

International Symposium on Computer Architecture, 2020
Tamper-proof hardware designs present a great challenge to computer architects. Most existing research limits hardware trusted computing base (TCB) to a CPU chip and anything off the CPU chip is vulnerable to probing and tampering.
Zhenyu Xu, Thomas Mauldin, Zheyi Yao, Shuyi Pei, Tao Wei, Qing Yang   +5 more
semanticscholar   +1 more source

TransPIM: A Memory-based Acceleration via Software-Hardware Co-Design for Transformer

International Symposium on High-Performance Computer Architecture, 2022
Transformer-based models are state-of-the-art for many machine learning (ML) tasks. Executing Transformer usually requires a long execution time due to the large memory footprint and the low data reuse rate, stressing the memory system while under ...
Minxuan Zhou, Weihong Xu, Jaeyoung Kang, Tajana Šimunić   +3 more
semanticscholar   +1 more source

CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism

International Symposium on High-Performance Computer Architecture, 2023
The attention mechanism is becoming an integral part of modern neural networks, bringing breakthroughs to Natural Language Processing (NLP) applications and even Computer Vision (CV) applications.
Haoran Wang, Haobo Xu, Ying Wang, Yinhe Han   +3 more
semanticscholar   +1 more source

LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference

International Symposium on Computer Architecture
The past year has witnessed the increasing popularity of Large Language Models (LLMs). Their unprecedented scale and associated high hardware cost have impeded their broader adoption, calling for efficient hardware designs. With the large hardware needed
Hengrui Zhang, August Ning, R. Prabhakar, D. Wentzlaff   +3 more
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A new golden age for computer architecture: Domain-specific hardware/software co-design, enhanced security, open instruction sets, and agile chip development

International Symposium on Computer Architecture, 2018
In the 1980s, Mead and Conway1 democratized chip design and high-level language programming surpassed assembly language programming, which made instruction set advances viable.
J. Hennessy
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Sibia: Signed Bit-slice Architecture for Dense DNN Acceleration with Slice-level Sparsity Exploitation

International Symposium on High-Performance Computer Architecture, 2023
Deep neural networks (DNNs) have achieved high performance in many AI fields such as 1-D language, 2-D image, and 3-D point cloud processing applications.
Dongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, H. Yoo   +4 more
semanticscholar   +1 more source