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A Hardware-Software Co-Design for the Discrete Gaussian Sampling of FALCON Digital Signature
IEEE International Symposium on Hardware Oriented Security and TrustSampling random values from a discrete Gaussian distribution with high precision is a major and computationally-intensive operation of emerging and existing cryptographic standards.
Emre Karabulut, Aydin Aysu
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International Symposium on High-Performance Computer Architecture
The brain-inspired Spiking Neural Network (SNN) has great potential to reduce energy consumption in AI applications. However, the state-of-the-art SNN algorithms focus on high accuracy and large sparsity by constructing complex neuron models with sparse ...
Ruixin Mao +4 more
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The brain-inspired Spiking Neural Network (SNN) has great potential to reduce energy consumption in AI applications. However, the state-of-the-art SNN algorithms focus on high accuracy and large sparsity by constructing complex neuron models with sparse ...
Ruixin Mao +4 more
semanticscholar +1 more source
International Symposium on High-Performance Computer Architecture, 2021
Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center.
H. Liao +6 more
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Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center.
H. Liao +6 more
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Hardware-Software Co-Design for Brain-Computer Interfaces
International Symposium on Computer Architecture, 2020Brain-computer interfaces (BCIs) offer avenues to treat neurological disorders, shed light on brain function, and interface the brain with the digital world.
I. Karageorgos +7 more
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Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems
International Symposium on High-Performance Computer Architecture, 2020As transistor scaling becomes increasingly more difficult to achieve, scaling the core count on a single GPU chip has also become extremely challenging.
Trinayan Baruah +9 more
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Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network
International Symposium on Computer Architecture, 2017Hardware acceleration of Deep Neural Networks (DNNs) aims to tame their enormous compute intensity. Fully realizing the potential of acceleration in this domain requires understanding and leveraging algorithmic properties of DNNs.
Hardik Sharma +7 more
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Insights into DeepSeek-V3: Scaling Challenges and Reflections on Hardware for AI Architectures
International Symposium on Computer ArchitectureThe rapid scaling of large language models (LLMs) has unveiled critical limitations in current hardware architectures, including constraints in memory capacity, computational efficiency, and interconnection bandwidth. DeepSeek-V3, trained on 2,048 NVIDIA
Chenggang Zhao +14 more
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Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON
IEEE International Symposium on Hardware Oriented Security and Trust, 2018Arvind Singh +3 more
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ACBuilder: A tool for hardware architecture security evaluation
IEEE International Symposium on Hardware Oriented Security and Trust, 2016Henrique Kawakami +4 more
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