A comparison of integration methods for single‐cell RNA sequencing data and ATAC sequencing data
Abstract Single‐cell genomics give us a new perspective to understand multivariate phenotypic and genetic effects at the cellular level. Recently, technologies have started measuring different modalities of individual cells, such as transcriptomes, epigenomes, metabolomes, and spatial profiling.
Yulong Kan+5 more
wiley +1 more source
A blockchain-based smart healthcare system for data protection. [PDF]
Adeniyi JK+6 more
europepmc +1 more source
Structure‐Aware Representation Learning for Effective Performance Prediction
ABSTRACT Application performance is a function of several unknowns stemming from the interactions between the application, runtime, OS, and underlying hardware, making it challenging to model performance using deep learning techniques, especially without a large labeled dataset. Collecting such labeled longitudinal datasets can take weeks. Intuitively,
Tarek Ramadan+4 more
wiley +1 more source
Research on Development Progress and Test Evaluation of Post-Quantum Cryptography. [PDF]
Zhang M+6 more
europepmc +1 more source
PIA-A secure and efficient identity authentication scheme in telemedicine via the PUF method. [PDF]
Wang X+5 more
europepmc +1 more source
A method to enhance privacy preservation in cloud storage through a three-layer scheme for computational intelligence in fog computing. [PDF]
Ojha S+6 more
europepmc +1 more source
Quantum-resilient software security: A fuzzy AHP-based assessment framework in the era of quantum computing. [PDF]
Almotiri SH.
europepmc +1 more source
An efficient ECC and fuzzy verifier based user authentication protocol for IoT enabled WSNs. [PDF]
Sudhakar T, Praveen R, Natarajan V.
europepmc +1 more source
A verifiably secure and robust authentication protocol for synergistically-assisted IoD deployment drones. [PDF]
Algarni AD, Innab N, Algarni F.
europepmc +1 more source
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Hash, Don't Cache (the Page Table)
ACM SIGMETRICS Performance Evaluation Review, 2016Radix page tables as implemented in the x86-64 architecture incur a penalty of four memory references for address translation upon each TLB miss. These 4 references become 24 in virtualized setups, accounting for 5%--90% of the runtime and thus motivating chip vendors to incorporate page walk caches (PWCs).
Yaniv, Idan, Tsafrir, Dan
openaire +4 more sources