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IEEE Spectrum, 2007
The Intel's Core 2 microprocessors, based on the latest 45-nanometer CMOS process technology have more transistors and run faster and cooler than microprocessors fabricated with the previous, 65-nm process generation. For compute-intensive music, video, and gaming applications, users will see a hefty performance increase.
Mark Bohr +3 more
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The Intel's Core 2 microprocessors, based on the latest 45-nanometer CMOS process technology have more transistors and run faster and cooler than microprocessors fabricated with the previous, 65-nm process generation. For compute-intensive music, video, and gaming applications, users will see a hefty performance increase.
Mark Bohr +3 more
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High-k Materials in Flash Memories
ECS Transactions, 2006The scaling down of Flash memories can be pursued using the conventional stacked gate architecture only with major changes of the active dielectrics, mainly the inter-poly dielectric (IPD).The required 4-6 nm EOT thickness for the IPD cannot be achieved by the conventional ONO (Oxide-Nitride-Oxide) technology which starts failing in the 10-12 nm range ...
Mauro Alessandri +15 more
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High-k Dielectrics Integration Prospects
ECS Meeting Abstracts, 2006Abstract not Available.
Stefan Kubicek +20 more
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Trapping in high-k dielectrics
Applied Physics Letters, 2010In this paper, an analytical model of trapping in high-k dielectrics is proposed. It starts from the general rate equation and relies on the hypothesis that the density of states involved in the capture mechanism follows a Fermi-like distribution. Thus, the energy depth of the trap level respect to the Fermi level is explicited in the model.
RAO, ROSARIO +2 more
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High-k Characterization by RFCV
ECS Meeting Abstracts, 2007Abstract not Available.
Enrique San Andres +7 more
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2013
Due to the need of increasing the gate capacitance of metal-oxide-semiconductor (MOS) devices, the layer thickness of the SiO2 gate dielectric is reducing to such thickness that the leakage current is becoming too large to control. Suitable high-oxides hence need to be found in order to replace the existing gate dielectric, because the thicker layer of
Silva, E. L., Santos, M. C.
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Due to the need of increasing the gate capacitance of metal-oxide-semiconductor (MOS) devices, the layer thickness of the SiO2 gate dielectric is reducing to such thickness that the leakage current is becoming too large to control. Suitable high-oxides hence need to be found in order to replace the existing gate dielectric, because the thicker layer of
Silva, E. L., Santos, M. C.
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2013
Interaction of different materials in the multilayer high-k/metal gate stacks results in the formation of structural defects in the high-k dielectric and interfacial SiO2 layer. This section discusses the impact that defects in intrinsic Hf-based dielectric layers have on the electron trapping process and concurrent defect generation occurring under ...
Chadwin D. Young, Gennadi Bersuker
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Interaction of different materials in the multilayer high-k/metal gate stacks results in the formation of structural defects in the high-k dielectric and interfacial SiO2 layer. This section discusses the impact that defects in intrinsic Hf-based dielectric layers have on the electron trapping process and concurrent defect generation occurring under ...
Chadwin D. Young, Gennadi Bersuker
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Realization of silicon carbide MIS capacitors with high-K and high-K stack dielectric
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014Silicon carbide MIS capacitors with high dielectric constant material and its stack has been designed and characterized using TCAD Sentaurus tools. Interface dipole theory on metal-dielectric interface has been used to determine the work function of gate metal on different dielectric materials.
E. Papanasam, Binsu J Kailath
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2003
Introduction The need for high-k gate dielectrics and materials requirement Deposition techniques ALCVD, MOCVD, PLD, MBE Characterization Physico-chemical characterization X-ray and electron spectroscopies Oxygen diffusion and thermal stability Defect characterization by ESR Band alignment determined by photo-injection Electrical characteristics Theory
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Introduction The need for high-k gate dielectrics and materials requirement Deposition techniques ALCVD, MOCVD, PLD, MBE Characterization Physico-chemical characterization X-ray and electron spectroscopies Oxygen diffusion and thermal stability Defect characterization by ESR Band alignment determined by photo-injection Electrical characteristics Theory
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Hafnium-based high-K dielectrics
IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)., 2005Hafnium-based high-K dielectrics such as HfO/sub 2/, HfON and HfSiON have attracted a great deal of attention because of their potential for successful integration into CMOS technology. However, channel mobility degradation, charge trapping and reliability are major concerns.
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