Results 1 to 10 of about 50 (47)
arXiv: Other Computer Science, 2008 Hardware synthesis is a general term used to refer to the processes involved in automatically generating a hardware design from its specification. High-level synthesis (HLS) could be defined as the translation from a behavioral description of the intended hardware circuit into a structural description similar to the compilation of programming languages
Adam Morawiec, Philippe Coussy
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Reclocking for high level synthesis [PDF]
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 1995 Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath ...
Pradip K. Jha +2 more
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Formal verification of high-level synthesis [PDF]
Proceedings of the ACM on Programming Languages, 2021 High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as ...
Yann Herklotz +3 more
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Probabilistic Scheduling in High-Level Synthesis
2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021 High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low- level hardware description. A key challenge in HLS tools is scheduling, i.e. determining the start time of all the operations in the untimed program. There are three approaches to scheduling: static, dynamic and hybrid.
Cheng, J +2 more
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Validating High-Level Synthesis [PDF]
, 2008 The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the process of generating Register Transfer Level (RTL) design from these initial high-level programs.
Sorin Lerner +2 more
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Reliability-Centric High-Level Synthesis [PDF]
Design, Automation and Test in Europe, 2005 Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and component shut-down. As a result, it is becoming necessary to treat reliability as a first-class
Tosun, S. +4 more
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A memory aware high level synthesis tool [PDF]
IEEE Computer Society Annual Symposium on VLSI, 2004 We introduce a new approach to take into account the memory architecture and the memory mapping in High- Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step.
Corre, Gwenole +3 more
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Affine Multibanking for High-Level Synthesis
, 2021 In the last decade, FPGAs appeared as a credible alternative for big data and high-performance computing applications. However, programming an FPGA is tedious: given a function to implement, the circuit configuration must be built from scratch by the developer.
Lasfar, Ilham +4 more
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Timing models for high-level synthesis [PDF]
Proceedings EURO-DAC '92: European Design Automation Conference, 2003 A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can
Chaiyakul, Viraphol +2 more
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User Guided High Level Synthesis [PDF]
, 1997 This paper presents a High Level Synthesis (HLS) method for specialized coprocessors in embedded systems. In recent years, the synthesis of hardware systems has moved to a higher level of abstraction, but the existing tools leave very little initiative to the designer.
Augé, Ivan +5 more
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