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Reclocking for high level synthesis [PDF]
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 1995 Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath ...
Pradip Jha, Nikil Dutt, Sri Parameswaran
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FPGA-Based Hardware/Software Co-Design of a Bio-Inspired SAT Solver
IEEE Access, 2020 For various kinds of Internet of Things (IoT) systems whose control rules can be expressed in a Satisfiability (SAT) problem, this work aims at realizing an IoT-oriented FPGA-based SAT solver leveraging a bio-inspired algorithm, AmoebaSAT, using a ...
Anh Hoang Ngoc Nguyen +2 more
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A High-Level Synthesis Approach for a RISC-V RV32I-Based System on Chip and Its FPGA Implementation
Engineering Proceedings, 2023 In this paper, we present a RISC-V RV32I-based system-on-chip (SoC) design approach using the Vivado high-level synthesis (HLS) tool. The proposed approach consists of three separate levels: The first one is an HLS design and simulation purely in C ...
Onur Toker
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BIST controller design with high-level synthesis
Dianzi Jishu Yingyong, 2018 MBIST(Memory Built-In Self-Test) technology has extensive application in the memory test. In view of the traditional BIST controller register transfer level description language design process is relatively complicated, special flexibility EDA tools to ...
Cai Hongyan +5 more
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Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis
IEEE Access, 2017 Using FPGA-based acceleration of high-performance computing (HPC) applications to reduce energy and power consumption is becoming an interesting option, thanks to the availability of high-level synthesis (HLS) tools that enable fast design cycles ...
Liang Ma +3 more
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Equivalence Checking of Scheduling in High-Level Synthesis Using Deep State Sequences
IEEE Access, 2019 By using high-level synthesis tools, electronic system level design provides a promising solution to fill the growing design productivity gap of high quality hardware systems.
Jian Hu +3 more
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AnyHLS: High-Level Synthesis With Partial Evaluation [PDF]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020 12 pages, 9 ...
Özkan, M. Akif +7 more
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Probabilistic Scheduling in High-Level Synthesis
2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021 High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low- level hardware description. A key challenge in HLS tools is scheduling, i.e. determining the start time of all the operations in the untimed program. There are three approaches to scheduling: static, dynamic and hybrid.
Cheng, J +2 more
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Efficient Fuzzy Controllers for FPGA using High Level Synthesis
Revista Elektrón, 2022 Fuzzy Logic Controllers (FLC) are control systems commonly used on problems where data is not accurate or its domain is not well-known. This is because instead of using complex mathematical models to work, they use a set of rules to evaluate data.
Luca Sarramone +2 more
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ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs
Computers, 2018 The end of Dennard scaling led to the use of heterogeneous multi-processor systems-on-chip (MPSoCs). Heterogeneous MPSoCs provide a high efficiency in terms of energy and performance due to the fact that each processing element can be optimized for an ...
Jens Rettkowski, Diana Göhringer
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