Results 11 to 20 of about 3,480,511 (346)
A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding
IEEE Access, 2023 Spiking Neural Networks (SNNs) are promising candidates for low-power and low-latency embedded artificial intelligence. However, those networks require event-based data produced by neuromorphic sensors which are not widely available, except for a few ...
Clemence Gillet +3 more
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IEEE Access, 2022 In this work, we present the design and implementation of an ultra-low latency Deep Reinforcement Learning (DRL) FPGA based accelerator for addressing hard real-time Mixed Integer Programming problems.
Gerasimos Gerogiannis +5 more
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Reclocking for high level synthesis [PDF]
Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 1995 Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath ...
Pradip Jha, Nikil Dutt, Sri Parameswaran
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An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators
IEEE Open Journal of Circuits and Systems, 2021 K-Nearest Neighbor (kNN) is an efficient algorithm used in many applications, e.g., text categorization, data mining, and predictive analysis. Despite having a high computational complexity, kNN is a candidate for hardware acceleration since it is a ...
Hamoud Younes +3 more
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Function‐level module sharing techniques in high‐level synthesis
ETRI Journal, 2020 High‐level synthesis (HLS), which automatically synthesizes a register‐transfer level (RTL) circuit from a behavioral description written in a high‐level programming language such as C/C++, is becoming a more popular technique for improving design ...
Hiroki Nishikawa +4 more
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An Improved Blind Zone Channelization Structure and Rapid Implementation Method
Micromachines, 2023 The paper proposes an enhanced design for broadband digital receivers that aims to improve signal capture probability, real-time performance, and the hardware development cycle.
Ziliang Jia, Hongxia Liu
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Templatized Fused Vector Floating-Point Dot Product for High-Level Synthesis
Journal of Low Power Electronics and Applications, 2022 Machine-learning accelerators rely on floating-point matrix and vector multiplication kernels. To reduce their cost, customized many-term fused architectures are preferred, which improve the latency, power, and area of the designs.
Dionysios Filippas +2 more
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A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator
Technologies, 2018 Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism.
Dimitris Tsiktsiris +2 more
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Hardware design of convolution calculation module based on systolic array
Dianzi Jishu Yingyong, 2020 Aiming at the long broadcast, much fan in/fan out data path problem brought by high parullelism in the process of the Field Programmable Gate Array(FPGA) to realize the convolution computation in convolutional neural network, this paper adopts pulse ...
Wang Chunlin, Tan Kejun
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Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
Applied Sciences, 2021 Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity.
Adam Milik, Marcin Kubica, Dariusz Kania
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