Results 21 to 30 of about 3,480,511 (346)
FPGA Based Real Time Simulations of the Face Milling Process
IEEE Access, 2020 The article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met.
Michal R. Mazur +2 more
doaj +1 more source
IEEE Access, 2020 Heterogeneous computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator that best matches its ...
Mostafa W. Numan +3 more
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Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs
IEEE Access, 2022 Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories
Giovanni Brignone +3 more
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Adaptive digital beamformer intellectual property based on high-level synthesis
The Journal of Engineering, 2019 Adaptive digital beamformer (ADBF) is effective in suppressing unexpected interferences arriving at the antenna array. An ADBF intellectual property (IP) using the floating point data type has been developed with high-level synthesis (HLS) technology ...
Shengxiang Zhu +3 more
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Efficient Fuzzy Controllers for FPGA using High Level Synthesis
Revista Elektrón, 2022 Fuzzy Logic Controllers (FLC) are control systems commonly used on problems where data is not accurate or its domain is not well-known. This is because instead of using complex mathematical models to work, they use a set of rules to evaluate data.
Luca Sarramone +2 more
doaj +1 more source
Design Space Exploration of LDPC Decoders Using High-Level Synthesis
IEEE Access, 2017 Today, high-level synthesis (HLS) tools are being touted as a means to perform rapid prototyping and shortening the long development cycles needed to produce hardware designs in register transfer level (RTL).
Joao Andrade +8 more
doaj +1 more source
Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM
IEEE Access, 2018 Closed-loop stimulation of many neurological disorders, such as epilepsy, is an emerging technology and regarded as a promising alternative for surgical and drug treatment.
Hongda Wang, Weiwei Shi, Chiu-Sing Choy
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The Journal of Engineering, 2017 Owing to aggressive shrinking in nanometre scale as well as faster devices, particle strike manifesting itself into transient fault spanning multiple cycle and multiple units will be the centre-focus of application specific datapath generated through ...
Anirban Sengupta, Deepak Kachave
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Probabilistic Scheduling in High-Level Synthesis
2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2021 High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low- level hardware description. A key challenge in HLS tools is scheduling, i.e. determining the start time of all the operations in the untimed program. There are three approaches to scheduling: static, dynamic and hybrid.
Cheng, J +2 more
openaire +2 more sources
AnyHLS: High-Level Synthesis With Partial Evaluation [PDF]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020 12 pages, 9 ...
Özkan, M. Akif +7 more
openaire +3 more sources