Results 111 to 120 of about 1,369 (159)
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Compilers for instruction-level parallelism
Computer, 1997Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance. What technical challenges must compiler writers meet to better use ILP? Instruction level parallelism allows a sequence of instructions derived from a sequential program to be parallelized for execution on multiple pipelined ...
Thomas M. Conte +5 more
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Instruction-Level Parallel Processing
Science, 1991The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and
Joseph A. Fisher, B. Ramakrishna Rau
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Instruction-level parallelism in Prolog
Proceedings of the 19th annual international symposium on Computer architecture - ISCA '92, 1992The demand of increasing computation power for symbolic processing has given a strong impulse to the development of ASICs dedicated to the execution of prolog. Unlike past microcoded implementation based on the Warren machine model, novel trends in high performance Prolog processors suggest the implementation of RISC-based processors committed to ...
DE GLORIA, ALESSANDRO, P. Faraboschi
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Exploiting instruction-level parallelism
ACM SIGMICRO Newsletter, 1992The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented.
Shashank Nemawarkar +2 more
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Modeling Instruction-Level Parallelism for WCET Evaluation [PDF]
12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), 2006 The estimation of the Worst-Case Execution Time of hard real-time applications becomes very hard as more and more complex processors are used in realtime systems. In modern architectures, estimating the execution time of a single basic block is not trivial due to possible timing anomalies linked to out-of-order execution.
Jonathan Barre +3 more
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A combinatorial architecture for instruction-level parallelism
Microprocessors and Microsystems, 1998Abstract The work presents a new principle for microprocessor design based on a pairwise-balanced combinatorial arrangement of processing and memory elements. The proposed apparatus uses two operand instructions so that a set of executable machine instructions is partitioned by these address pairs.
Efraim Berkovich, Simon Berkovich
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An architecture for high instruction level parallelism
Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences, 2002High instruction level parallelism (ILP) can only be achieved when data flow and control flow constraints have been removed or reduced. Data flow constraints, not inherent in the original code, arise from lack of sufficient resources for initiation and execution of multiple instructions concurrently.
S. Arya, H. Sachs, S. Duvvuru
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Instruction level test for parallel multipliers
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test ...
Ma Lin, Gao Yan
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Instruction-level parallelism for reconfigurable computing [PDF]
, 1998 Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural
Timothy J. Callahan, John Wawrzynek
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A hierarchical approach to instruction-level parallelization
International Journal of Parallel Programming, 1995In this paper we extend Percolation Scheduling (PS) to navigate through a hierarchical version of the Control Flow Graph (CFG) representation of a VLIW program. This extension retains the completeness of PS by allowing the “normal” PS transformations to be applied incrementally between adjacent instructions but also enablesnonincremental code motions ...
Alexandru Nicolau, Steven Novack
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