Results 121 to 130 of about 1,369 (159)
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Scalable Instruction-Level Parallelism
2004This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for out-of-order instruction issue; it defines the model and explores implementations issues.
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Extraction of massive instruction level parallelism
ACM SIGARCH Computer Architecture News, 1993Our goal is to dramatically increase the performance of uniprocessors through the exploitation of instruction level parallelism, i.e. that parallelism which exists amongst the machine instructions of a program. Speculative execution may help a lot, but, it is argued, both branch prediction and eager execution are insufficient to achieve performances in
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Available instruction-level parallelism for superscalar and superpipelined machines [PDF]
ACM SIGARCH Computer Architecture News, 1989 Superscalar machines can issue several instructions per cycle. Superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latency of any functional unit. In this paper these two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism. A parameterizable
Norman P. Jouppi, David W. Wall
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Hybrid predication model for instruction level parallelism
Proceedings 16th International Parallel and Distributed Processing Symposium, 2002This paper presents a hybrid predication model in analogy to the delayed branching technique with overlapped delayed slots by integrating two different predication models. Predicated-execution is considered a promising branch handling technique. A few models have been proposed for predicated-execution, the most known model has succeeded to provide ILP ...
A. M. M. Ashmawy +2 more
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Instruction-Level Parallelism and Uniprocessor Architecture
1999Research in Instruction-Level Parallelism (ILP) is concerned with architectural innovations in the processor to expose parallelism between the execution of instructions. Of course, the relationship with the research on the memory hierarchy and on compiler optimisation techniques is very strong.
Mateo Valero, Pascal Sainrat
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Exploiting instruction level parallelism with the DS architecture
Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, 2002A new architecture, DS, for exploiting instruction level parallelism is proposed in this paper. DS splits the program into two instruction substreams with the dominant one navigating the control flow and the subsidiary one carrying out the rest of the computational task.
G.B. Adam, Yinong Zhang
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Instruction-Level Parallelism and Computer Architecture
2001The papers presented in this combined topic consider issues related to the broad theme of computer architecture research. The program reflects the current emphasis of research on the exploitation of instruction-level parallelism and thread-level parallelism, with the papers presented covering several important aspects on both approaches: branch ...
Guang R. Gao +7 more
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A superscalar architecture to exploit instruction level parallelism
Microprocessors and Microsystems, 1997Abstract If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent and which therefore can be issued and executed in parallel at run time.
Bruce Christianson +4 more
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Parallel Computer Architecture and Instruction-Level Parallelism
2002Welcome to this topic of the Euro-Par conference held this year in picturesque Paderborn, Germany. I was extremely honored to serve as the global chair for these sessions on Parallel Computer Architecture and Instruction-Level Parallelism and I look forward to meeting all practitioners of the field, researchers, and students at the conference.
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A Study of Techniques to Increase Instruction Level Parallelisms
Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control, 2018Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different ...
Michael Opoku Agyeman +1 more
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