Results 171 to 180 of about 220,437 (272)

Instruction Level Parallelism and Memory Synchronization

Rupam Sardar
openalex   +2 more sources

Massively Parallel Tensor Network State Algorithms on Hybrid CPU-GPU Based Architectures. [PDF]

J Chem Theory Comput
Menczer A, Legeza Ö.
europepmc   +1 more source

Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection. [PDF]

Micromachines (Basel)
Xu J, Pu H, Wang D.
europepmc   +1 more source

Computational Modeling of Ganglion Cell Bicolor Opponent Receptive Fields and FPGA Adaptation for Parallel Arrays. [PDF]

Biomimetics (Basel)
Wei H, Yao W.
europepmc   +1 more source

Accelerated Method for Simulating the Solidification Microstructure of Continuous Casting Billets on GPUs. [PDF]

Materials (Basel)
Wang J, Liu X, Li Y, Mao R.
europepmc   +1 more source

Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms

ACM Symposium on Parallelism in Algorithms and Architectures, 2007
Timothy Furtak, J. N. Amaral, R. Niewiadomski   +2 more
semanticscholar   +1 more source

kalis: a modern implementation of the Li & Stephens model for local ancestry inference in R. [PDF]

BMC Bioinformatics
Aslett LJM, Christ RR.
europepmc   +1 more source

A Hybrid Scale-Up and Scale-Out Approach for Performance and Energy Efficiency Optimization in Systolic Array Accelerators. [PDF]

Micromachines (Basel)
Sun H, Shen J, Zhang C, Liu H.
europepmc   +1 more source

An efficient parallelization technique for the coupled problems of fluid, gas and plasma mechanics in the grid environment. [PDF]

Sci Rep
Zinchenko A, Fernandez-Gamiz U, Redchyts D, Gorna O, Bilousova T.   +4 more
europepmc   +1 more source

Abstract representations emerge in human hippocampal neurons during inference. [PDF]

Nature
Courellis HS, Minxha J, Cardenas AR, Kimmel DL, Reed CM, Valiante TA, Salzman CD, Mamelak AN, Fusi S, Rutishauser U.   +9 more
europepmc   +1 more source