Massively Parallel Tensor Network State Algorithms on Hybrid CPU-GPU Based Architectures. [PDF]
Menczer A, Legeza Ö.
europepmc +1 more source
Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection. [PDF]
Xu J, Pu H, Wang D.
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Computational Modeling of Ganglion Cell Bicolor Opponent Receptive Fields and FPGA Adaptation for Parallel Arrays. [PDF]
Wei H, Yao W.
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Accelerated Method for Simulating the Solidification Microstructure of Continuous Casting Billets on GPUs. [PDF]
Wang J, Liu X, Li Y, Mao R.
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Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms
Timothy Furtak+2 more
semanticscholar +1 more source
kalis: a modern implementation of the Li & Stephens model for local ancestry inference in R. [PDF]
Aslett LJM, Christ RR.
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A Hybrid Scale-Up and Scale-Out Approach for Performance and Energy Efficiency Optimization in Systolic Array Accelerators. [PDF]
Sun H, Shen J, Zhang C, Liu H.
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An efficient parallelization technique for the coupled problems of fluid, gas and plasma mechanics in the grid environment. [PDF]
Zinchenko A+4 more
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Abstract representations emerge in human hippocampal neurons during inference. [PDF]
Courellis HS+9 more
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