Results 211 to 220 of about 220,437 (272)
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Compilers for instruction-level parallelism
Computer, 1997Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance. What technical challenges must compiler writers meet to better use ILP? Instruction level parallelism allows a sequence of instructions derived from a sequential program to be parallelized for execution on multiple pipelined ...
Thomas M. Conte+5 more
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Instruction-level parallelism for reconfigurable computing [PDF]
Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural
Timothy J. Callahan, John Wawrzynek
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A combinatorial architecture for instruction-level parallelism
Abstract The work presents a new principle for microprocessor design based on a pairwise-balanced combinatorial arrangement of processing and memory elements. The proposed apparatus uses two operand instructions so that a set of executable machine instructions is partitioned by these address pairs.
Efraim Berkovich, Simon Berkovich
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Scalable Instruction-Level Parallelism
International Conference / Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation, 2004This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for out-of-order instruction issue; it defines the model and explores implementations issues.
C. Jesshope
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Combining optimization for cache and instruction-level parallelism
Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique, 2002Current architectural trends in instruction-level parallelism (ILP) have significantly increased the computational power of microprocessors. As a result, the demands on the memory system have increased dramatically. Not only do compilers need to be concerned with finding ILP to utilize machine resources effectively, but they also need to be concerned ...
S. Carr
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Exploring Efficient Microservice Level Parallelism
IEEE International Parallel and Distributed Processing Symposium, 2022The microservice architecture has recently become a driving trend in the cloud by disaggregating a monolithic application into many scenario-oriented service blocks (microservices). The decomposition process results in a highly dynamic execution scenario,
Xinkai Wang+5 more
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Instruction-Level Parallel Processing
Science, 1991The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and
Joseph A. Fisher, B. Ramakrishna Rau
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The limits of instruction level parallelism in SPEC95 applications
ACM SIGARCH Computer Architecture News, 1999Trevor Mudge+3 more
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Exploiting instruction-level parallelism
ACM SIGMICRO Newsletter, 1992The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented.
Shashank Nemawarkar+2 more
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Modeling Instruction-Level Parallelism for WCET Evaluation [PDF]
The estimation of the Worst-Case Execution Time of hard real-time applications becomes very hard as more and more complex processors are used in realtime systems. In modern architectures, estimating the execution time of a single basic block is not trivial due to possible timing anomalies linked to out-of-order execution.
Jonathan Barre+3 more
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