Results 211 to 220 of about 224,259 (279)

Design and Implementation of a Lightweight and Energy-Efficient Semantic Segmentation Accelerator for Embedded Platforms. [PDF]

Micromachines (Basel)
Li H, Li J, Li B, Miao Z, Lu S.
europepmc   +1 more source

InfectA-Chat, an Arabic Large Language Model for Infectious Diseases: Comparative Analysis.

JMIR Med Inform
Selcuk Y, Kim E, Ahn I.
europepmc   +1 more source

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An architecture for high instruction level parallelism

Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences, 2002
High instruction level parallelism (ILP) can only be achieved when data flow and control flow constraints have been removed or reduced. Data flow constraints, not inherent in the original code, arise from lack of sufficient resources for initiation and execution of multiple instructions concurrently.
S. Arya, H. Sachs, S. Duvvuru
openaire   +3 more sources

Instruction-level parallelism for reconfigurable computing [PDF]

International Conference on Field-Programmable Logic and Applications, 1998
Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural
Timothy J. Callahan, John Wawrzynek
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Compilers for instruction-level parallelism

Computer, 1997
Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance. What technical challenges must compiler writers meet to better use ILP? Instruction level parallelism allows a sequence of instructions derived from a sequential program to be parallelized for execution on multiple pipelined ...
Thomas M. Conte, J. Dehnert, C.L. Thompson, M.S. Schlansker, Kemal Ebcioglu, J.Z. Fang   +5 more
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Scalable Instruction-Level Parallelism

International Conference / Workshop on Embedded Computer Systems: Architectures, Modeling and Simulation, 2004
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for out-of-order instruction issue; it defines the model and explores implementations issues.
C. Jesshope
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Combining optimization for cache and instruction-level parallelism

Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique, 2002
Current architectural trends in instruction-level parallelism (ILP) have significantly increased the computational power of microprocessors. As a result, the demands on the memory system have increased dramatically. Not only do compilers need to be concerned with finding ILP to utilize machine resources effectively, but they also need to be concerned ...
S. Carr
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A combinatorial architecture for instruction-level parallelism

Microprocessors and Microsystems, 1998
Abstract The work presents a new principle for microprocessor design based on a pairwise-balanced combinatorial arrangement of processing and memory elements. The proposed apparatus uses two operand instructions so that a set of executable machine instructions is partitioned by these address pairs.
Efraim Berkovich, Simon Berkovich
openalex   +3 more sources