Results 211 to 220 of about 189,345 (270)
Some of the next articles are maybe not open access.
Exploring Efficient Microservice Level Parallelism
IEEE International Parallel and Distributed Processing Symposium, 2022The microservice architecture has recently become a driving trend in the cloud by disaggregating a monolithic application into many scenario-oriented service blocks (microservices). The decomposition process results in a highly dynamic execution scenario,
Xinkai Wang +5 more
semanticscholar +1 more source
International Conference on Communication and Electronics Systems, 2021
The knowledge of multi-core programming helps in the utilisation of multiple cores at the same time to execute a task and thereby achieving scalability and increase in performance.
Lekshmi Nair
semanticscholar +1 more source
The knowledge of multi-core programming helps in the utilisation of multiple cores at the same time to execute a task and thereby achieving scalability and increase in performance.
Lekshmi Nair
semanticscholar +1 more source
Instruction-Level Parallel Processing
Science, 1991The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and
J A, Fisher, R, Rau
openaire +2 more sources
Exploiting instruction-level parallelism
ACM SIGMICRO Newsletter, 1992The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented.
P. Lenir +2 more
openaire +1 more source
Instruction level test for parallel multipliers
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test ...
null Ma Lin, null Gao Yan
openaire +1 more source
A combinatorial architecture for instruction-level parallelism
Microprocessors and Microsystems, 1998Abstract The work presents a new principle for microprocessor design based on a pairwise-balanced combinatorial arrangement of processing and memory elements. The proposed apparatus uses two operand instructions so that a set of executable machine instructions is partitioned by these address pairs.
E. Berkovich, S. Berkovich
openaire +1 more source
Modeling Instruction-Level Parallelism for WCET Evaluation
12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), 2006The estimation of the Worst-Case Execution Time of hard real-time applications becomes very hard as more and more complex processors are used in realtime systems. In modern architectures, estimating the execution time of a single basic block is not trivial due to possible timing anomalies linked to out-of-order execution.
J. Barre +3 more
openaire +1 more source
Parallel Computer Architecture and Instruction-Level Parallelism
2002Welcome to this topic of the Euro-Par conference held this year in picturesque Paderborn, Germany. I was extremely honored to serve as the global chair for these sessions on Parallel Computer Architecture and Instruction-Level Parallelism and I look forward to meeting all practitioners of the field, researchers, and students at the conference.
openaire +1 more source
Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism
2004Parallel architecture design and ILP architectures are important topics at the core of every parallel system, affecting the total system performance in fundamental ways. Instruction-Level Parallelism has for decades represented a foremost performance booster of leading edge computing systems.
Kemal Ebcioglu +3 more
openaire +3 more sources
Reconfigurable Instruction-Level Parallel Processor Architecture
2003This paper proposes an instruction-level parallel (ILP) processor with architecture reconfigurability. The processor can employ the optimal architecture to applications without loosing generality. Instruction-level parallelism is achieved by expanding the number of PUs depending on its load. Required features of reconfigurable hardware devices for such
Toshiyuki Ito +4 more
openaire +1 more source