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Instruction level test for parallel multipliers

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test ...
Ma Lin, Gao Yan
openaire   +2 more sources

A hierarchical approach to instruction-level parallelization

International Journal of Parallel Programming, 1995
In this paper we extend Percolation Scheduling (PS) to navigate through a hierarchical version of the Control Flow Graph (CFG) representation of a VLIW program. This extension retains the completeness of PS by allowing the “normal” PS transformations to be applied incrementally between adjacent instructions but also enablesnonincremental code motions ...
Alexandru Nicolau, Steven Novack
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Interlock collapsing ALU for increased instruction-level parallelism

open access: closed[1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25, 1992
N. Malik   +2 more
openalex   +2 more sources

Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors

Computer/law journal, 2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction level parallelism (ILP). The most significant problem with this approach is
K. Bousias, N. Hasasneh, C. Jesshope
semanticscholar   +1 more source

Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

Micro, 1995
Exploitation of instruction-level parallelism is an effective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism.
J. Davidson, S. Jinturkar
semanticscholar   +1 more source

Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring

IEEE Trans. Computers, 1994
Computer architectures are using increased degrees of instruction-level machine parallelism to achieve higher performance, e.g., superpipelined, superscalar and very long instruction word (VLIW) processors. Full utilization of such machine parallelism is
M. Schuette, John Paul Shen
semanticscholar   +1 more source

Extraction of massive instruction level parallelism

ACM SIGARCH Computer Architecture News, 1993
Our goal is to dramatically increase the performance of uniprocessors through the exploitation of instruction level parallelism, i.e. that parallelism which exists amongst the machine instructions of a program. Speculative execution may help a lot, but, it is argued, both branch prediction and eager execution are insufficient to achieve performances in
openaire   +2 more sources

Hybrid predication model for instruction level parallelism

Proceedings 16th International Parallel and Distributed Processing Symposium, 2002
This paper presents a hybrid predication model in analogy to the delayed branching technique with overlapped delayed slots by integrating two different predication models. Predicated-execution is considered a promising branch handling technique. A few models have been proposed for predicated-execution, the most known model has succeeded to provide ILP ...
A. M. M. Ashmawy   +2 more
openaire   +2 more sources

Exploiting instruction level parallelism with the DS architecture

Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, 2002
A new architecture, DS, for exploiting instruction level parallelism is proposed in this paper. DS splits the program into two instruction substreams with the dominant one navigating the control flow and the subsidiary one carrying out the rest of the computational task.
G.B. Adam, Yinong Zhang
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Instruction-Level Parallelism and Computer Architecture

2001
The papers presented in this combined topic consider issues related to the broad theme of computer architecture research. The program reflects the current emphasis of research on the exploitation of instruction-level parallelism and thread-level parallelism, with the papers presented covering several important aspects on both approaches: branch ...
Guang R. Gao   +7 more
openaire   +2 more sources

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