Results 221 to 230 of about 224,259 (279)
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FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism
ACM Transactions on Reconfigurable Technology and Systems, 2023Coarse-grained reconfigurable architectures (CGRAs) have emerged as promising accelerators due to their high flexibility and energy efficiency. However, existing open source works often lack integration of CGRAs with CPU systems and corresponding ...
Yunhui Qiu +6 more
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Exploring Efficient Microservice Level Parallelism
IEEE International Parallel and Distributed Processing Symposium, 2022The microservice architecture has recently become a driving trend in the cloud by disaggregating a monolithic application into many scenario-oriented service blocks (microservices). The decomposition process results in a highly dynamic execution scenario,
Xinkai Wang +5 more
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The limits of instruction level parallelism in SPEC95 applications
ACM SIGARCH Computer Architecture News, 1999Trevor Mudge +3 more
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Instruction-Level Parallel Processing
Science, 1991The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and
Joseph A. Fisher, B. Ramakrishna Rau
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Exploiting instruction-level parallelism
ACM SIGMICRO Newsletter, 1992The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented.
Shashank Nemawarkar +2 more
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Interlock collapsing ALU for increased instruction-level parallelism
[1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25, 1992 N. Malik +2 more
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Modeling Instruction-Level Parallelism for WCET Evaluation [PDF]
12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), 2006 The estimation of the Worst-Case Execution Time of hard real-time applications becomes very hard as more and more complex processors are used in realtime systems. In modern architectures, estimating the execution time of a single basic block is not trivial due to possible timing anomalies linked to out-of-order execution.
Jonathan Barre +3 more
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Instruction level test for parallel multipliers
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test ...
Ma Lin, Gao Yan
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An efficient global resource constrained technique for exploiting instruction level parallelism [PDF]
, 1992 A new Global Resource-constrained Percolation (GRiP) scheduling technique is presented for exploiting instruction level parallelism. Other techniques that have been proposed either have been prohibitively expensive in terms of computation or have limited
Alexandru Nicolau, Steven Novack
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A hierarchical approach to instruction-level parallelization
International Journal of Parallel Programming, 1995In this paper we extend Percolation Scheduling (PS) to navigate through a hierarchical version of the Control Flow Graph (CFG) representation of a VLIW program. This extension retains the completeness of PS by allowing the “normal” PS transformations to be applied incrementally between adjacent instructions but also enablesnonincremental code motions ...
Alexandru Nicolau, Steven Novack
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