Results 221 to 230 of about 189,345 (270)

Hybrid predication model for instruction level parallelism

Proceedings 16th International Parallel and Distributed Processing Symposium, 2002
This paper presents a hybrid predication model in analogy to the delayed branching technique with overlapped delayed slots by integrating two different predication models. Predicated-execution is considered a promising branch handling technique. A few models have been proposed for predicated-execution, the most known model has succeeded to provide ILP ...
A.M.M. Ashmawy, H.F. Ismail, A.H. Fahmy
openaire   +1 more source

Instruction-Level Parallelism and Computer Architecture

2001
The papers presented in this combined topic consider issues related to the broad theme of computer architecture research. The program reflects the current emphasis of research on the exploitation of instruction-level parallelism and thread-level parallelism, with the papers presented covering several important aspects on both approaches: branch ...
Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk Muller, Rizos Sakellariou, André Seznec   +7 more
openaire   +1 more source

Extraction of massive instruction level parallelism

ACM SIGARCH Computer Architecture News, 1993
Our goal is to dramatically increase the performance of uniprocessors through the exploitation of instruction level parallelism, i.e. that parallelism which exists amongst the machine instructions of a program. Speculative execution may help a lot, but, it is argued, both branch prediction and eager execution are insufficient to achieve performances in
openaire   +1 more source

A hierarchical approach to instruction-level parallelization

International Journal of Parallel Programming, 1995
In this paper we extend Percolation Scheduling (PS) to navigate through a hierarchical version of the Control Flow Graph (CFG) representation of a VLIW program. This extension retains the completeness of PS by allowing the “normal” PS transformations to be applied incrementally between adjacent instructions but also enablesnonincremental code motions ...
Steven Novack, Alexandru Nicolau
openaire   +1 more source

Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units

International Conference on Application of Concurrency to System Design, 2017
Anoop Bhagyanath, K. Schneider
semanticscholar   +1 more source

A Two-Way Loop Algorithm for Exploiting Instruction-Level Parallelism in Memory System

Communication Systems and Applications, 2014
S. Misra, A. A. Alfa, O. S. Adewale, Michael Abogunde Akogbe, Mikail Olayemi Olaniyi   +4 more
semanticscholar   +1 more source

An Approach for Compiler Optimization to Exploit Instruction Level Parallelism

, 2014
R. Kumar, P. K. Singh
semanticscholar   +1 more source

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Journal of Supercomputing, 2011
B. Abderazek, Masashi Masuda, A. Canedo, Kenichi Kuroda   +3 more
semanticscholar   +1 more source

Parallelism of intestinal secretory IgA shapes functional microbial fitness

Nature, 2021
Tim Rollenske, Lukas Mürner, Stephan von Gunten   +2 more
exaly  

Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architecture

, 2012
D. Kiran, S. Gurunarayanan, Faizan Khaliq, Abhijeet Nawal   +3 more
semanticscholar   +1 more source