Results 231 to 240 of about 220,437 (272)

Parallel Computer Architecture and Instruction-Level Parallelism

2002
Welcome to this topic of the Euro-Par conference held this year in picturesque Paderborn, Germany. I was extremely honored to serve as the global chair for these sessions on Parallel Computer Architecture and Instruction-Level Parallelism and I look forward to meeting all practitioners of the field, researchers, and students at the conference.
openaire   +2 more sources

A Study of Techniques to Increase Instruction Level Parallelisms

Proceedings of the 2nd International Symposium on Computer Science and Intelligent Control, 2018
Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different ...
Michael Opoku Agyeman, Liliana Margarita Espinosa Jimenez   +1 more
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A superscalar architecture to exploit instruction level parallelism

Microprocessors and Microsystems, 1997
Abstract If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent and which therefore can be issued and executed in parallel at run time.
Bruce Christianson, Richard D. Potter, G.B. Steven, Roger Collins, Fleur L. Steven   +4 more
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Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism

2004
Parallel architecture design and ILP architectures are important topics at the core of every parallel system, affecting the total system performance in fundamental ways. Instruction-Level Parallelism has for decades represented a foremost performance booster of leading edge computing systems.
Wolfgang Karl, André Seznec, Kemal Ebcioglu, Marco Aldinucci   +3 more
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Branch merging for effective exploitation of instruction-level parallelism

ACM SIGMICRO Newsletter, 1992
In this paper, we propose a novel algorithm for merging branches in VLIW and superscalar architectures employing multi-way branch mechanisms. The branch merging problem is to find sets of branches that, can be merged and executed concurrently. The advantages of using branch merging are: (1) to reduce the number of stalls due to branches and (2) to ...
Chung-Ta King, Chien-Ming Chen, Yuun-Yen Chen   +2 more
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Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units

International Conference on Application of Concurrency to System Design, 2017
Anoop Bhagyanath, K. Schneider
semanticscholar   +1 more source

Reconfigurable Instruction-Level Parallel Processor Architecture

2003
This paper proposes an instruction-level parallel (ILP) processor with architecture reconfigurability. The processor can employ the optimal architecture to applications without loosing generality. Instruction-level parallelism is achieved by expanding the number of PUs depending on its load. Required features of reconfigurable hardware devices for such
Toshiyuki Ito, Yuuichi Okuyama, Mayumi Ichikawa, Kentaro Ono, Kenichi Kuroda   +4 more
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Instruction Level Parallelism

Springer US, 2016
Alex Aiken, Utpal Banerjee, A. Kejariwal, Alexandru Nicolau   +3 more
semanticscholar   +1 more source

A Two-Way Loop Algorithm for Exploiting Instruction-Level Parallelism in Memory System

Communication Systems and Applications, 2014
S. Misra, A. A. Alfa, O. S. Adewale, Michael Abogunde Akogbe, Mikail Olayemi Olaniyi   +4 more
semanticscholar   +1 more source

An Approach for Compiler Optimization to Exploit Instruction Level Parallelism

, 2014
R. Kumar, P. K. Singh
semanticscholar   +1 more source