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Reconfigurable Instruction-Level Parallel Processor Architecture
2003This paper proposes an instruction-level parallel (ILP) processor with architecture reconfigurability. The processor can employ the optimal architecture to applications without loosing generality. Instruction-level parallelism is achieved by expanding the number of PUs depending on its load. Required features of reconfigurable hardware devices for such
Toshiyuki Ito +4 more
openaire +2 more sources
A Two-Way Loop Algorithm for Exploiting Instruction-Level Parallelism in Memory System
Communication Systems and Applications, 2014S. Misra +4 more
semanticscholar +1 more source
An Approach for Compiler Optimization to Exploit Instruction Level Parallelism
, 2014R. Kumar, P. K. Singh
semanticscholar +1 more source
Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architecture
, 2012D. Kiran +3 more
semanticscholar +1 more source
A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)
Microprocessors and microsystems, 2010Yu Zhang +4 more
semanticscholar +1 more source
Parallelism of intestinal secretory IgA shapes functional microbial fitness
Nature, 2021Tim Rollenske +2 more
exaly
Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit
International Symposium on Computer Architecture, 2016M. Yoon +4 more
semanticscholar +1 more source
Genome-wide parallelism underlies contemporary adaptation in urban lizards
Proceedings of the National Academy of Sciences of the United States of America, 2023Shane C Campbell-Staton +2 more
exaly