Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading [PDF]
ACM Transactions on Computer Systems, 1997 J. Lo +5 more
semanticscholar +2 more sources
Exploiting Instruction Level Parallelism In Processors By Caching Scheduled Groups [PDF]
Conference Proceedings. The 24th Annual International Symposium on Computer Architecture, 1997 R. Nair, Martin E. Hopkins
semanticscholar +2 more sources
Automatically Extracting GPU Instruction-Level Parallelism
, 2014 James A. Jablin
openaire +2 more sources
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs
IEEE Open Journal of Circuits and Systems, 2021 ConvAix is an application-specific instruction-set processor (ASIP) that enables the energy-efficient processing of convolutional neural networks (CNNs) while retaining substantial flexibility through its instruction-set architecture (ISA) based design ...
Andreas Bytyn +2 more
doaj +1 more source
Instruction-Level Parallelism and Parallelizing Compilation (Dagstuhl Seminar 99161)
, 1999 Arvind, D. K. +4 more
openaire +4 more sources
Optimization of Digital Signal Transformation Functions in Multicluster VLIW DSP [PDF]
Jisuanji gongcheng, 2016 According to the characteristics of BWDSP100 processor’s architecture,this paper presents several practical ways to improve the performance of digital signal transformation functions in Digital Signal Processor(DSP) function library,including using ...
ZHEN Yang,GU Naijie,YE Hong
doaj +1 more source
Realization and Application of Shenwei Simultaneous Multithreading Functional Simulator [PDF]
Jisuanji gongcheng, 2016 imultaneous Multithreading(SMT) allows irrelevant instructions execute synchronously from multiple threads.It achieves the combination of Thread-level Parallelism(TLP) and Instruction-level Parallelism(ILP),enhances the performance of processor further ...
CHEN Weijian,GUO Yong,YIN Fei
doaj +1 more source
A Single Instruction Multiple Data Vectorization Reduction Method [PDF]
Jisuanji gongcheng, 2017 Single Instruction Multiple Data(SIMD) aims at exploiting the data-level parallelism of multimedia and scientific calculation.The true dependence caused by reduction operation hinders exploring data-level parallelism.But different architecture and ...
HAN Lin,GAO Wei,WANG Dong,WANG Pengxiang,LI Yingying
doaj +1 more source
Design of Deep Learning VLIW Processor for Image Recognition
Xibei Gongye Daxue Xuebao, 2020 In order to adapt the application demands of high resolution images recognition and efficient processing of localization in aviation and aerospace fields, and to solve the problem of insufficient parallelism in existing researches, an extensible ...
doaj +1 more source
An astute LVQ approach using neural network for the prediction of conditional branches in pipeline processor [PDF]
EAI Endorsed Transactions on Scalable Information Systems, 2021 Nowadays, microprocessors use the deep pipeline to execute multiple instructions per cycle. The frequency and behavior of conditional instructions mainly affect the performance of instruction-level parallelism.
Sweety Nain, Prachi Chaudhary
doaj +1 more source