Results 41 to 50 of about 220,437 (272)
EKSPLOITASI INSTRUCTION-LEVEL PARALELLISM (ILP) PADA UNIPROCESSOR [PDF]
, 2006 Saat ini para ilmuwan melakukan banyak penelitian dalam rangka meningkatkan performa komputer. Beberapa diantaranya mengkhususkan diri dalam mengembangkan parallelism baik pada Bit-Level Parallelism, Instruction-Level Parallelism maupun dengan konsep ...
Effendi, Rustam +1 more
core +3 more sources
Hardware schemes for early register release [PDF]
, 2002 Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the size and number of ports of the ...
González Colás, Antonio María +3 more
core +1 more source
A case for merging the ILP and DLP paradigms [PDF]
, 1998 The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its ...
Espasa Sans, Roger +2 more
core +1 more source
IEEE Access, 2013 The adaptive Runge-Kutta (ARK) method on multi-general-purpose graphical processing units (GPUs) is used for solving large nonlinear systems of first-order ordinary differential equations (ODEs) with over ~ 10 000 variables describing a large genetic ...
Ahmad Al-Omari +3 more
doaj +1 more source
Register Saturation in Instruction Level Parallelism [PDF]
International Journal of Parallel Programming, 2005 The registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG.
openaire +3 more sources
Understanding the thermal implications of multicore architectures [PDF]
, 2007 Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level ...
Cai, Qiong +4 more
core +2 more sources
Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method
IEEE Access, 2020 CGRA (Coarse-grained Reconfigurable Architecture) has been widely considered as one of the most promising computing architectures to exploit spatial parallelism.
Jiang Sha +3 more
doaj +1 more source
Vectorization of Program Code Containing Low Probability Regions in Computational Geometry Problems
Современные информационные технологии и IT-образование, 2022 Improving application performance is an important practical task for supercomputer calculations. Along with parallelization of calculations between cluster nodes (for example, using MPI tools), as well as multithreaded programming (for example, using ...
Alexey Rybakov
doaj +1 more source
Sensors, 2017 This paper aims to develop a low-cost, high-performance and high-reliability computing system to process large-scale data using common data mining algorithms in the Internet of Things (IoT) computing environment.
Yuling Fang +4 more
doaj +1 more source
IEEE Access, 2023 In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed.
Netanel Shavit +4 more
doaj +1 more source