Results 41 to 50 of about 224,259 (279)
Register Saturation in Instruction Level Parallelism [PDF]
International Journal of Parallel Programming, 2005 The registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG.
openaire +3 more sources
Late allocation and early release of physical registers [PDF]
, 2004 The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the ...
González Colás, Antonio María +4 more
core +2 more sources
A case for merging the ILP and DLP paradigms [PDF]
, 1998 The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its ...
Espasa Sans, Roger +2 more
core +1 more source
Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method
IEEE Access, 2020 CGRA (Coarse-grained Reconfigurable Architecture) has been widely considered as one of the most promising computing architectures to exploit spatial parallelism.
Jiang Sha +3 more
doaj +1 more source
Hardware schemes for early register release [PDF]
, 2002 Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the size and number of ports of the ...
González Colás, Antonio María +3 more
core +1 more source
Vectorization of Program Code Containing Low Probability Regions in Computational Geometry Problems
Современные информационные технологии и IT-образование, 2022 Improving application performance is an important practical task for supercomputer calculations. Along with parallelization of calculations between cluster nodes (for example, using MPI tools), as well as multithreaded programming (for example, using ...
Alexey Rybakov
doaj +1 more source
Strategy of microscopic parallelism for Bitplane Image Coding [PDF]
, 2015 Recent years have seen the upraising of a new type of processors strongly relying on the Single Instruction, Multiple Data (SIMD) architectural principle.
Aulí-Llinàs, Francesc +4 more
core +1 more source
Sensors, 2017 This paper aims to develop a low-cost, high-performance and high-reliability computing system to process large-scale data using common data mining algorithms in the Internet of Things (IoT) computing environment.
Yuling Fang +4 more
doaj +1 more source
From Physics Model to Results: An Optimizing Framework for Cross-Architecture Code Generation [PDF]
, 2013 Starting from a high-level problem description in terms of partial differential equations using abstract tensor notation, the Chemora framework discretizes, optimizes, and generates complete high performance codes for a wide range of compute ...
Blazewicz, Marek +8 more
core +4 more sources
Microarchitectural Characterization on a Mobile Workload
Applied Sciences, 2021 Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely
Woohyong Lee +3 more
doaj +1 more source