Results 51 to 60 of about 1,369 (159)

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

IEEE Access
The Single Instruction Multiple Data (SIMD) architecture, supported by various high-performance computing platforms, efficiently utilizes data-level parallelism.
Dheya Mustafa, Ruba Alkhasawneh, Fadi Obeidat, Ahmed S. Shatnawi   +3 more
doaj   +1 more source

Enhancing Fault Tolerance in High-Performance Computing: A Real Hardware Case Study on a RISC-V Vector Processing Unit

IEEE Open Journal of the Computer Society
High-Performance Computing (HPC) systems are designed for large-scale processing and complex dataset analysis leveraging scalability, efficiency, and parallelism, often integrating specialized hardware structures such as Vector Processing Units (VPUs ...
Marcello Barbirotta, Francesco Minervini, Carlos Rojas Morales, Adrian Cristal, Osman Unsal, Mauro Olivieri   +5 more
doaj   +1 more source

Exploiting deep learning accelerators for neuromorphic workloads

Neuromorphic Computing and Engineering
Spiking neural networks (SNNs) have achieved orders of magnitude improvement in terms of energy consumption and latency when performing inference with deep learning workloads.
Pao-Sheng Vincent Sun, Alexander Titterton, Anjlee Gopiani, Tim Santos, Arindam Basu, Wei D Lu, Jason K Eshraghian   +6 more
doaj   +1 more source

Employing register channels for the exploitation of instruction level parallelism [PDF]

ACM SIGPLAN Notices, 1990
A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the use of shared register channels as the communication mechanism among processors in a multiprocessor chip.
openaire   +3 more sources

P-CORE: Exploring RISC-V Packed-SIMD Extension for CNNs

IEEE Access
In today’s technological landscape, embedded and IoT devices face escalating demands for performance and power efficiency in inference tasks employing Convolution Neural Networks (CNNs).
Muhammad Ali, Ensieh Aliagha, Mahmoud Elnashar, Diana Gohringer   +3 more
doaj   +1 more source

Power estimation on functional level for programmable processors [PDF]

Advances in Radio Science, 2004
In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW ...
M. Schneider, H. Blume, T. G. Noll
doaj  

Twelve Times Faster yet Accurate: A New State‐Of‐The‐Art in Radiation Schemes via Performance and Spectral Optimization

Journal of Advances in Modeling Earth Systems
Radiation schemes are critical components of Earth system models that need to be both efficient and accurate. Despite the use of approximations such as 1D radiative transfer, radiation can account for a large share of the runtime of expensive climate ...
Peter Ukkonen, Robin J. Hogan
doaj   +1 more source

Exploiting Thread-Level and Instruction-Level Parallelism to Cluster Mass Spectrometry Data using Multicore Architectures. [PDF]

Netw Model Anal Health Inform Bioinform, 2014
Saeed F, Hoffert JD, Pisitkun T, Knepper MA.   +3 more
europepmc   +1 more source

Fast noisy long read alignment with multi-level parallelism. [PDF]

BMC Bioinformatics
Xia Z, Yang C, Peng C, Guo Y, Guo Y, Tang T, Cui Y.   +6 more
europepmc   +1 more source

Instruction-Level Parallelism and Parallelizing Compilation (Dagstuhl Seminar 99161) [PDF]

, 1999
Arvind, D. K., Ebcioglu, Kemal, Lengauer, Christian, Pingali, Keshav, Schreiber, Robert S.   +4 more
openaire   +3 more sources