Results 51 to 60 of about 220,437 (272)
POWER: Parallel Optimizations With Executable Rewriting [PDF]
, 2011 The hardware industry's rapid development of multicore and many core hardware has outpaced the software industry's transition from sequential to parallel programs. Most applications are still sequential, and many cores on parallel machines remain unused.
Arora, Nipun +4 more
core +2 more sources
Microarchitectural Characterization on a Mobile Workload
Applied Sciences, 2021 Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely
Woohyong Lee +3 more
doaj +1 more source
The impact of exploiting instruction-level parallelism on shared-memory multiprocessors [PDF]
IEEE Trans. Computers, 1999 Current microprocessors incorporate techniques to aggressively exploit instruction-level parallelism (ILP). This paper evaluates the impact of such processors on the performance of shared-memory multiprocessors, both without and with the latency-hiding ...
Vijay S. Pai +3 more
openalex +2 more sources
Late allocation and early release of physical registers [PDF]
, 2004 The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the ...
González Colás, Antonio María +4 more
core +2 more sources
, 1993 Instruction-level parallelism (ILP) is a set of processor and compiler design techniques that speed up program execution via the parallel execution of individual RISC-style operations, such as memory loads and stores, integer additions, and floating-point multiplications.
Joseph A. Fisher, B. Ramakrishna Rau
openaire +2 more sources
A Pipeline-Based ODE Solving Framework
IEEE AccessThe traditional parallel solving methods of ordinary differential equations (ODE) are mainly classified into task-parallelism, data-parallelism, and instruction-level parallelism.
Ruixia Cao, Shangjun Hou, Lin Ma
doaj +1 more source
IEEE Open Journal of Power Electronics, 2020 System-level electromagnetic transient (EMT) simulation of large-scale power converters with high-order nonlinear semiconductor switch models remains a challenge albeit it is essential for design preview. In this work, a multi-layer hierarchical modeling
Ning Lin, Ruimin Zhu, Venkata Dinavahi
doaj +1 more source
Strategy of microscopic parallelism for Bitplane Image Coding [PDF]
, 2015 Recent years have seen the upraising of a new type of processors strongly relying on the Single Instruction, Multiple Data (SIMD) architectural principle.
Aulí-Llinàs, Francesc +4 more
core +1 more source
Scalable IC Platform for Smart Cameras
EURASIP Journal on Advances in Signal Processing, 2005 Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the ...
Harry Broers +3 more
doaj +1 more source
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems
Sensors, 2012 The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems.
Hu He, Xu Yang
doaj +1 more source