Results 51 to 60 of about 224,259 (279)
IEEE Access, 2023 In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed.
Netanel Shavit +4 more
doaj +1 more source
Thread partitioning and value prediction for exploiting speculative thread-level parallelism [PDF]
, 2004 Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find.
González Colás, Antonio María +2 more
core +2 more sources
, 1993 Instruction-level parallelism (ILP) is a set of processor and compiler design techniques that speed up program execution via the parallel execution of individual RISC-style operations, such as memory loads and stores, integer additions, and floating-point multiplications.
Joseph A. Fisher, B. Ramakrishna Rau
openaire +2 more sources
A Pipeline-Based ODE Solving Framework
IEEE AccessThe traditional parallel solving methods of ordinary differential equations (ODE) are mainly classified into task-parallelism, data-parallelism, and instruction-level parallelism.
Ruixia Cao, Shangjun Hou, Lin Ma
doaj +1 more source
IEEE Open Journal of Power Electronics, 2020 System-level electromagnetic transient (EMT) simulation of large-scale power converters with high-order nonlinear semiconductor switch models remains a challenge albeit it is essential for design preview. In this work, a multi-layer hierarchical modeling
Ning Lin, Ruimin Zhu, Venkata Dinavahi
doaj +1 more source
Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures [PDF]
, 1999 We exploit the existence of distant parallelism that future compilers could detect and characterise its performance under simultaneous multithreading architectures.
Ayguadé Parra, Eduard +4 more
core +1 more source
Scalable IC Platform for Smart Cameras
EURASIP Journal on Advances in Signal Processing, 2005 Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the ...
Harry Broers +3 more
doaj +1 more source
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems
Sensors, 2012 The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems.
Hu He, Xu Yang
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Understanding the thermal implications of multicore architectures [PDF]
, 2007 Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations by exploiting thread-level ...
Cai, Qiong +4 more
core +2 more sources
Design Principles for Sparse Matrix Multiplication on the GPU
, 2018 We implement two novel algorithms for sparse-matrix dense-matrix multiplication (SpMM) on the GPU. Our algorithms expect the sparse input in the popular compressed-sparse-row (CSR) format and thus do not require expensive format conversion.
A Tiskin +11 more
core +1 more source