Results 61 to 70 of about 224,259 (279)

A Method to Detect Hazards in Pipeline Processor

MATEC Web of Conferences, 2017
In order to improve the throughput of the processors, pipeline technique is widely used to implement the instruction-level parallelism. However, this technique also leads to data hazards which has a great influence on the performance. This paper proposed
He Yihui, Wan Han, Jiang Bo, Gao Xiaopeng   +3 more
doaj   +1 more source

EKSPLOITASI INSTRUCTION-LEVEL PARALELLISM (ILP) PADA UNIPROCESSOR [PDF]

, 2006
Saat ini para ilmuwan melakukan banyak penelitian dalam rangka meningkatkan performa komputer.  Beberapa diantaranya mengkhususkan diri dalam mengembangkan parallelism baik pada Bit-Level Parallelism, Instruction-Level Parallelism maupun dengan konsep ...
Effendi, Rustam, Kuspriyanto, Kuspriyanto   +1 more
core   +3 more sources

Perovskite Microwires for Room Temperature Exciton‐Polariton Neural Network

Advanced Materials, EarlyView.
Exciton‐polaritons are explored as a novel platform for optical neuromorphic computing at room temperature using a monocrystalline perovskite waveguide. Demonstrating non‐equilibrium Bose‐Einstein condensation, this work achieves machine learning tasks such as classification and object detection, marking a key advance toward energy‐efficient, practical
Andrzej Opala, Krzysztof Tyszka, Mateusz Kędziora, Magdalena Furman, Amir Rahmani, Stanisław Świerczewski, Marek Ekielski, Anna Szerling, Michał Matuszewski, Barbara Piętka   +9 more
wiley   +1 more source

Investigating performance metrics for container-based HPC environments using x86 and OpenPOWER systems

Journal of Cloud Computing: Advances, Systems and Applications, 2023
Container-based High-Performance Computing (HPC) is changing the way computation is performed and reproduced without sacrificing the raw performance compared to hypervisor-assisted virtualization technologies.
Animesh Kuity, Sateesh K. Peddoju
doaj   +1 more source

A kinematically Bifurcated Metamaterial for Integrated Logic Operation and Computing

Advanced Science, EarlyView.
A family of 2n‐side kinematic polygonal modules with n decoupled inputs and 2n extreme configurations via kinematic bifurcation is proposed. It allows integrating seven basic logic gates on a quadrilateral module. Moreover, a minimized Parallel Computing Sum of Products function is developed, enabling all 2‐bit arithmetic (including division ...
Kaili Xi, Jingsong Wei, Xiao Zhang, Jiayao Ma, Zhong You, Changqing Chen, Yan Chen   +6 more
wiley   +1 more source

Efficient Prefetch and Issue Scheduling Approaches for Simultaneous Multithreading Applied to Superscalar RISC-V Processor

IEEE Access
Thread level parallelism (TLP) is a common approach to achieve parallelism where Instruction level parallelism (ILP) is insufficient. Hardware multithreading is a prevalent approach in the micro-architecture layer for tolerating long events such as ...
Hananya Ribo, Shlomo Greenberg
doaj   +1 more source

Accelerating SAR Image Registration Using Swarm-Intelligent GPU Parallelization

IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, 2020
Image registration is an important processing step in synthetic aperture radar (SAR) image applications, such as change detection, and elevation extraction.
Yingbing Liu, Yingcheng Zhou, Yongsheng Zhou, Lixiang Ma, Bingnan Wang, Fan Zhang   +5 more
doaj   +1 more source

Enhancing Synaptic Plasticity in Strontium Titanate‐Based Sensory Processing Devices: A Study on Oxygen Vacancy Modulation and Performance in Artificial Neural Networks

Advanced Intelligent Discovery, EarlyView.
This article presents the artificial synapse based on strontium titanate thin films via spin‐coating followed by forming gas annealing to introduce oxygen vacancies. Characterizations (X‐ray photoelectron spectroscopy, electron paramagnetic resonance, Ultraviolet photoelectron spectroscopy (UPS)) confirm increased oxygen vacancies and downward energy ...
Fandi Chen, Zijian Feng, Shuo Zhang, Jie Min, Long Hu, Tianxu Huang, Tingting Mei, Jiyun Kim, Beining Dong, Xinyu Ma, Tao Yin, Jintao Wang, Peiyuan Guan, Tao Wan, Chun‐Ho Lin, Zhi Li, Dewei Chu   +16 more
wiley   +1 more source

Instruction-level parallel processing: History, overview, and perspective [PDF]

The Journal of Supercomputing, 1993
Instruction-level parallelism (ILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design.
Joseph A. Fisher, B. Ramakrishna Rau
openaire   +2 more sources

Symbolic Reservoir Computing within Memristive Crossbar Arrays as a Cellular Automata

Advanced Intelligent Systems, EarlyView.
In quest of a neuro‐symbolic system with both strong intelligent computing capability and better explainability, a memristor crossbar array‐based cellular automata (symbolic model) for reservoir computing (neural network) is proposed and experimentally demonstrated using an algorithm–hardware codesign approach.
Yunpeng Guo, Chenfei Miao, Xinxin Wang, Xue Liu, Cheng Ma, Lidan Wang, Shukai Duan, Wenrui Duan, Huanglong Li   +8 more
wiley   +1 more source