Results 61 to 70 of about 220,437 (272)
Modulo scheduling with reduced register pressure [PDF]
Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for software pipelining.
Ayguadé Parra, Eduard+3 more
core +2 more sources
A Method to Detect Hazards in Pipeline Processor
In order to improve the throughput of the processors, pipeline technique is widely used to implement the instruction-level parallelism. However, this technique also leads to data hazards which has a great influence on the performance. This paper proposed
He Yihui+3 more
doaj +1 more source
AI‐Driven Defect Engineering for Advanced Thermoelectric Materials
This review presents how AI accelerates the design of defect‐tuned thermoelectric materials. By integrating machine learning with high‐throughput data and physics‐informed representations, it enables efficient prediction of thermoelectric performance from complex defect landscapes.
Chu‐Liang Fu+9 more
wiley +1 more source
Container-based High-Performance Computing (HPC) is changing the way computation is performed and reproduced without sacrificing the raw performance compared to hypervisor-assisted virtualization technologies.
Animesh Kuity, Sateesh K. Peddoju
doaj +1 more source
From Physics Model to Results: An Optimizing Framework for Cross-Architecture Code Generation [PDF]
Starting from a high-level problem description in terms of partial differential equations using abstract tensor notation, the Chemora framework discretizes, optimizes, and generates complete high performance codes for a wide range of compute ...
Blazewicz, Marek+8 more
core +4 more sources
Superior Electromechanical Power at Rare‐Earth Manipulated Glassy Morphotropic Phase Transitions
An effective physical approach named Rare‐earth Manipulated Glassy Morphotropic Phase Transitions has been experimentally developed and theoretically validated to achieve significant enhancements of 135% and 50% in electrostrain and elastic modulus of lead‐free ferroelectrics respectively, further enabling the significant boost of requisite driving ...
Le Zhang+12 more
wiley +1 more source
Thread level parallelism (TLP) is a common approach to achieve parallelism where Instruction level parallelism (ILP) is insufficient. Hardware multithreading is a prevalent approach in the micro-architecture layer for tolerating long events such as ...
Hananya Ribo, Shlomo Greenberg
doaj +1 more source
Accelerating SAR Image Registration Using Swarm-Intelligent GPU Parallelization
Image registration is an important processing step in synthetic aperture radar (SAR) image applications, such as change detection, and elevation extraction.
Yingbing Liu+5 more
doaj +1 more source
On the efficiency of reductions in µ-SIMD media extensions [PDF]
Many important multimedia applications contain a significant fraction of reduction operations. Although, in general, multimedia applications are characterized for having high amounts of Data Level Parallelism, reductions and accumulations are difficult ...
Corbal San Adrián, Jesús+2 more
core +1 more source
This article presents the artificial synapse based on strontium titanate thin films via spin‐coating followed by forming gas annealing to introduce oxygen vacancies. Characterizations (X‐ray photoelectron spectroscopy, electron paramagnetic resonance, Ultraviolet photoelectron spectroscopy (UPS)) confirm increased oxygen vacancies and downward energy ...
Fandi Chen+16 more
wiley +1 more source