Results 61 to 70 of about 189,345 (270)
Thread level parallelism (TLP) is a common approach to achieve parallelism where Instruction level parallelism (ILP) is insufficient. Hardware multithreading is a prevalent approach in the micro-architecture layer for tolerating long events such as ...
Hananya Ribo, Shlomo Greenberg
doaj +1 more source
This study achieves anisotropic thermal expansion tuning in Nd2(Co1‐xFex)17‐yCry compounds via a magnetoelastic strategy. Variable‐temperature synchrotron X‐ray diffraction reveals that increased Fe content induces switchable lattice responses. Compositional control reduces the volume expansion coefficient αV by 20% (x═0.7) and modulates TC (442–625 K),
Jiayuan Li +8 more
wiley +1 more source
In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed.
Netanel Shavit +4 more
doaj +1 more source
RRAM Variability Harvesting for CIM‐Integrated TRNG
This work demonstrates a compute‐in‐memory‐compatible true random number generator that harvests intrinsic cycle‐to‐cycle variability from a 1T1R RRAM array. Parallel entropy extraction enables high‐throughput bit generation without dedicated circuits. This approach achieves NIST‐compliant randomness and low per‐bit energy, offering a scalable hardware
Ankit Bende +4 more
wiley +1 more source
This study introduces a real‐time light detection and ranging‐camera fusion framework for vehicle detection and tracking. Using a Gaussian mixture model‐based association and improved affinity metrics, the method enhances tracking reliability in dynamic conditions.
Muhammad Adeel Altaf, Min Young Kim
wiley +1 more source
The Potential for a GPU-Like Overlay Architecture for FPGAs
We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation.
Jeffrey Kingyens, J. Gregory Steffan
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Securing Generative Artificial Intelligence with Parallel Magnetic Tunnel Junction True Randomness
True random numbers can protect generative artificial intelligence (GAI) models from attacks. A highly parallel, spin‐transfer torque magnetic tunnel junction‐based system is demonstrated that generates high‐quality, energy‐efficient random numbers.
Youwei Bao, Shuhan Yang, Hyunsoo Yang
wiley +1 more source
Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit
Multithreading is widely used in microcontroller unit (MCU) chips. Multithreaded hardware is composed of multiple identical single threads and provides instructions to different threads.
Mao-Hsu Yen +5 more
doaj +1 more source
Container-based High-Performance Computing (HPC) is changing the way computation is performed and reproduced without sacrificing the raw performance compared to hypervisor-assisted virtualization technologies.
Animesh Kuity, Sateesh K. Peddoju
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Review of Memristors for In‐Memory Computing and Spiking Neural Networks
Memristors uniquely enable energy‐efficient, brain‐inspired computing by acting as both memory and synaptic elements. This review highlights their physical mechanisms, integration in crossbar arrays, and role in spiking neural networks. Key challenges, including variability, relaxation, and stochastic switching, are discussed, alongside emerging ...
Mostafa Shooshtari +2 more
wiley +1 more source

