Results 71 to 80 of about 220,437 (272)
Instruction-level parallel processing: History, overview, and perspective [PDF]
The Journal of Supercomputing, 1993 Instruction-level parallelism (ILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design.
Joseph A. Fisher, B. Ramakrishna Rau
openaire +2 more sources
Object oriented execution model (OOM) [PDF]
, 2011 This paper considers implementing the Object Oriented Programming Model directly in the hardware to serve as a base to exploit object-level parallelism, speculation and heterogeneous computing.
Cristal Kestelman, Adrián +5 more
core
Thread partitioning and value prediction for exploiting speculative thread-level parallelism [PDF]
, 2004 Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find.
González Colás, Antonio María +2 more
core +2 more sources
Multi‐Diseases Detection with Memristive System on Chip
Advanced Intelligent Systems, EarlyView.A robust disease detection system, which is capable of the early prevention of acute myocardial infarction and the detection of liver cancer, is implemented on a memristive system‐on‐chip (SoC). A fully integrated SoC is utilized to ensure the system's portability, low latency, high accuracy, and energy efficiency for medical analysis.
Zihan Wang +7 more
wiley +1 more source
The Potential for a GPU-Like Overlay Architecture for FPGAs
International Journal of Reconfigurable Computing, 2011 We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation.
Jeffrey Kingyens, J. Gregory Steffan
doaj +1 more source
Nanomechanical Systems for Reservoir Computing Applications
Advanced Intelligent Systems, EarlyView.Nanoelectromechanical systems (NEMS) are known for their strong nonlinear response, which can be conducive for reservoir computing. In this work, the authors build an NEMS‐based reservoir and investigate the classification accuracy as a function of drive levels and operation points.
Enise Kartal +7 more
wiley +1 more source
An Automatic Instruction-Level Parallelization of Machine Code
Advances in Electrical and Computer Engineering, 2018 Prevailing multicores and novel manycores have made a great challenge of modern day - parallelization of embedded software that is still written as sequential. In this paper, automatic code parallelization is considered, focusing on developing a parallelization tool at the binary level as well as on the validation of this approach.
Miroslav Popovic +2 more
openaire +3 more sources
Design Principles for Sparse Matrix Multiplication on the GPU
, 2018 We implement two novel algorithms for sparse-matrix dense-matrix multiplication (SpMM) on the GPU. Our algorithms expect the sparse input in the popular compressed-sparse-row (CSR) format and thus do not require expensive format conversion.
A Tiskin +11 more
core +1 more source
Journal of Experimental Zoology Part A: Ecological and Integrative Physiology, EarlyView.ABSTRACT The ability of organisms to effectively respond to challenges is critical for survival. We investigated how an acute stressor affected corticosterone, mitochondrial function, and DNA oxidative damage in a wild population of Leach's storm‐petrels (Hydrobates leucorhous).
Kayla E. Lichtner +10 more
wiley +1 more source
Chip Design of Multithreaded and Pipelined RISC-V Microcontroller Unit
Engineering ProceedingsMultithreading is widely used in microcontroller unit (MCU) chips. Multithreaded hardware is composed of multiple identical single threads and provides instructions to different threads.
Mao-Hsu Yen +5 more
doaj +1 more source