Results 71 to 80 of about 189,345 (270)

Step‐Efficient Parallel Implementation of n‐bit Full Adders Using Stateful Logic in Memristor Crossbar Arrays

Advanced Intelligent Systems, EarlyView.
A step‐efficient stateful logic architecture is demonstrated using a fabricated 32 × 32 memristor crossbar array, enabling parallel n‐bit full adder operations directly in memory. By optimizing load resistance and voltage configurations, the circuit achieves reliable NIMP, AND, and OR logic operations with minimized computational steps, enhanced ...
Jinwoo Park, Jungjin Lee, Sangwook Youn, Hyungjin Kim   +3 more
wiley   +1 more source

Accelerating SAR Image Registration Using Swarm-Intelligent GPU Parallelization

IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, 2020
Image registration is an important processing step in synthetic aperture radar (SAR) image applications, such as change detection, and elevation extraction.
Yingbing Liu, Yingcheng Zhou, Yongsheng Zhou, Lixiang Ma, Bingnan Wang, Fan Zhang   +5 more
doaj   +1 more source

Instruction-Level Parallelism and Processor Architecture [PDF]

, 2000
This year, the Euro-Par conference is being held in beautiful Munich, Germany. I am very honored to welcome you to the instruction level parallelism and pro- cessor architecture sessions of Euro-Par 2000!
openaire   +1 more source

Exploiting instruction-level parallelism : a constructive approach

, 1998
Luiz C. V. dos Santos
openaire   +3 more sources

Supramolecular Host‐Guest Complexation Dynamics by Cost‐Efficient Electronic Structure Methods

Chemistry – A European Journal, EarlyView.
We present a cost‐effective multilevel workflow for the kinetic profiling of host–guest systems, illustrated with cucurbit[6]uril and alkylammonium cations. The method combines rapid docking and reaction path searches at the semi‐empirical level, with refinement of the results using modern density functional theory, accurately reproducing experiment ...
Thomas Gasevic, Christoph Plett, Lukas Wittmann, Iago Neira, Carlos Peinador, Marcos D. García, Andreas Hansen   +6 more
wiley   +1 more source

Forecasting New Employment Using Nonrepresentative Online Job Advertisements With an Application to the Italian and EU Labor Market

Journal of Forecasting, EarlyView.
ABSTRACT Using online job advertisement data improves the timeliness and granularity depth of analysis in the labor market in domains not covered by official data. Specifically, its variation over time may be used as an anticipator of official employment variations.
Pietro Giorgio Lovaglio, Mario Mezzanzanica   +1 more
wiley   +1 more source

Corticosterone and Mitochondrial Efficiency Are Associated With Changes in DNA Oxidative Damage During an Acute Stress Response in Leach's Storm‐Petrels (Hydrobates leucorhous)

Journal of Experimental Zoology Part A: Ecological and Integrative Physiology, EarlyView.
ABSTRACT The ability of organisms to effectively respond to challenges is critical for survival. We investigated how an acute stressor affected corticosterone, mitochondrial function, and DNA oxidative damage in a wild population of Leach's storm‐petrels (Hydrobates leucorhous).
Kayla E. Lichtner, Jack K. Dziubek, Nicole A. Joseph, Sarah E. Chapman, Tori J. Chace, Dongxiao Sun, Zachary T. Bitzer, Antoine Stier, Robert A. Mauck, Patricia L. Jones, Mark F. Haussmann   +10 more
wiley   +1 more source

Fetch unit design for scalable simultaneous multithreading (ScSMT)

Journal of Computer Science and Technology, 2001
Continuous IC process enhancements make possible to integrate on a single chip the re-sources required for simultaneously executing multiple control flows or threads, exploiting different levels of thread-level parallelism: application-, function-, and ...
Juan Carlos Moure, Dolores Rexachs del Rosario, Emilio Luque Fadón   +2 more
doaj  

Instruction-Level Parallelism

, 1997
Exploitation of potential parallelism is obviously a major source of code optimization. This chapter therefore focusses on DSP-specific techniques, which aim at parallelization of generated vertical machine code. In the first part, we consider the area of memory address generation.
openaire   +1 more source

Instruction scheduling for instruction level parallel processors [PDF]

Proceedings of the IEEE, 2001
Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures.
P. Faraboschi, J.A. Fisher, C. Young
openaire   +1 more source