Results 101 to 110 of about 45,362 (262)

A high-performance tensor computing unit for deep learning acceleration

Chip
The increasing complexity of neural network applications has led to a demand for higher computational parallelism and more efficient synchronization in artificial intelligence (AI) chips. To achieve higher performance and lower power, a comprehensive and
Qiang Zhou, Tieli Sun, Taoran Shen, York Xue   +3 more
doaj   +1 more source

Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers

, 2019
Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum
Chong, Fred T., Gokhale, Pranav, Hoffman, Henry, Leung, Nelson, Rossi, Zane, Schuster, David I., Shi, Yunong   +6 more
core   +1 more source

Fecal corticosterone metabolite levels in two closely related rodent species in a sub‐Mediterranean environment

Wildlife Biology, EarlyView.
Glucocorticoids regulate many physiological functions and play an important role in coping with challenging stimuli. The non‐invasive assessment of glucocorticoids is increasingly used as a tool to evaluate individual and population health status in wild animals.
Carlo Cinque, Cristina Bencini, Paola Bartolommei, Andrea Bonacchi, Stefania Gasperini, Emiliano Manzo, Roberto Cozzolino   +6 more
wiley   +1 more source

The Effects of Human Presence, Restraint, and Stressed Neighbors on Corticosterone Levels in Domesticated Budgerigars (Melopsittacus undulatus)

Zoo Biology, EarlyView.
Female budgerigars (Melopsittacus undulatus) did not significantly elevate their plasma corticosterone levels in response to human presence at the beginning of the experiment. However, plasma corticosterone was significantly elevated by restraint stress, the return of a neighbor that received restraint stress, and human presence at the end of the ...
Dustin G. Reichard, Kelly V. Summers
wiley   +1 more source

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

IEEE Access
The Single Instruction Multiple Data (SIMD) architecture, supported by various high-performance computing platforms, efficiently utilizes data-level parallelism.
Dheya Mustafa, Ruba Alkhasawneh, Fadi Obeidat, Ahmed S. Shatnawi   +3 more
doaj   +1 more source

Loo.py: transformation-based code generation for GPUs and CPUs

, 2014
Today's highly heterogeneous computing landscape places a burden on programmers wanting to achieve high performance on a reasonably broad cross-section of machines.
Asanovic K., Ellson J., Rubinsteyn A.
core   +1 more source

Parameter Identification of Photovoltaic Models Using an Enhanced INFO Algorithm

CAAI Transactions on Intelligence Technology, EarlyView.
ABSTRACT Photovoltaic (PV) systems are electrical systems designed to convert solar energy into electrical energy. As a crucial component of PV systems, harsh weather conditions, photovoltaic panel temperature and solar irradiance influence the power output of photovoltaic cells.
Ying Chen, Peng Min, Huiling Chen, Cheng Tao, Zeye Long, Ali Asghar Heidari, Shuihua Wang, Yudong Zhang   +7 more
wiley   +1 more source

Percolation scheduling with resource constraints [PDF]

, 1989
This paper presents a new approach to resource-constrained compiler extraction of fine-grain parallelism, targeted towards VLIW supercomputers, and in particular, the IBM VLIW (Very Large Instruction Word) processor.
Ebciogiu, Kemal, Nicolau, Alexandru
core  

Enhancing Fault Tolerance in High-Performance Computing: A Real Hardware Case Study on a RISC-V Vector Processing Unit

IEEE Open Journal of the Computer Society
High-Performance Computing (HPC) systems are designed for large-scale processing and complex dataset analysis leveraging scalability, efficiency, and parallelism, often integrating specialized hardware structures such as Vector Processing Units (VPUs ...
Marcello Barbirotta, Francesco Minervini, Carlos Rojas Morales, Adrian Cristal, Osman Unsal, Mauro Olivieri   +5 more
doaj   +1 more source

Survey on Combinatorial Register Allocation and Instruction Scheduling

, 2018
Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler.
Lozano, Roberto Castañeda, Schulte, Christian   +1 more
core