Exploiting Thread-Level and Instruction-Level Parallelism to Cluster Mass Spectrometry Data using Multicore Architectures. [PDF]
Netw Model Anal Health Inform Bioinform, 2014 Saeed F +3 more
europepmc +3 more sources
Topic 8 Parallel Computer Architecture and Instruction-Level Parallelism [PDF]
, 2003 Parallel computer architecture and instruction-level parallelism are hot topics at Euro-Par conferences, since these techniques are present in most contemporary computing systems. At Euro-Par 2003, 18 papers were submitted to the topic, from which 1 distinguished, 4 regular and 4 short papers were accepted.
Stamatis Vassiliadis +3 more
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Software thread integration for instruction-level parallelism [PDF]
ACM Transactions on Embedded Computing Systems, 2013 Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt high-performance architectures like VLIW (Very-Long Instruction Word).
Won So, Alexander G. Dean
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Cimple: instruction and memory level parallelism [PDF]
, 2018 To appear in PACT ...
Vladimir Kiriansky +3 more
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Scalable instruction-level parallelism through tree-instructions [PDF]
Proceedings of the 11th international conference on Supercomputing - ICS '97, 1997 We describe a representation of instruction-level parallelism which does not require checking dependencies at run-time, and which is suitable for processor implementations with varying issuewidth. In this approach, a program is represented as a sequence of tree-instructions, each containing multiple primitive operations and executable either in one or ...
Jaime H. Moreno, Mayan Moudgil
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Instruction-Level Parallelism and Uniprocessor Architecture [PDF]
, 1999 Research in Instruction-Level Parallelism (ILP) is concerned with architectural innovations in the processor to expose parallelism between the execution of instructions. Of course, the relationship with the research on the memory hierarchy and on compiler optimisation techniques is very strong.
Pascal Sainrat, Mateo Valero
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Realizing the Calculation of a Fully Normalized Associated Legendre Function Based on an FPGA [PDF]
SensorsA large number of fully normalized associated Legendre function (fnALF) calculations are required to compute Earth’s gravity field elements using ultra high-order gravity field coefficient models.
Yuxiang Fang, Qingbin Wang, Yichao Yang
doaj +2 more sources
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs
IEEE Open Journal of Circuits and Systems, 2021 ConvAix is an application-specific instruction-set processor (ASIP) that enables the energy-efficient processing of convolutional neural networks (CNNs) while retaining substantial flexibility through its instruction-set architecture (ISA) based design ...
Andreas Bytyn +2 more
doaj +1 more source
An astute LVQ approach using neural network for the prediction of conditional branches in pipeline processor [PDF]
EAI Endorsed Transactions on Scalable Information Systems, 2021 Nowadays, microprocessors use the deep pipeline to execute multiple instructions per cycle. The frequency and behavior of conditional instructions mainly affect the performance of instruction-level parallelism.
Sweety Nain, Prachi Chaudhary
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