Results 191 to 200 of about 46,626 (281)

A study on an enhanced method for joint extraction of control intent and navigation information for smart city airport operations. [PDF]

Sci Rep
Yang Y, Yu Y, Wang X, Mao Y.
europepmc   +1 more source

Efficient motion estimation and discrete cosine transform implementation using the graphics processing units. [PDF]

PLoS One
Agha S, Jan F, Khan HA, Kaleem M, Khan M.   +4 more
europepmc   +1 more source

High Performance Soft Processor Architectures for Applications with Irregular Data- and Instruction-level Parallelism

, 2014
Kaveh Aasaraai
openalex   +1 more source

Exploiting instruction level parallelism in processors by caching scheduled groups [PDF]

, 1997
Ravi Nair, Martin Hopkins
openalex   +1 more source

A Novel Instruction Driven 1-D CNN Processor for ECG Classification. [PDF]

Sensors (Basel)
Deng J, Yang J, Wang X, Zhang X.
europepmc   +1 more source

Architecture Design of a Convolutional Neural Network Accelerator for Heterogeneous Computing Based on a Fused Systolic Array. [PDF]

Sensors (Basel)
Zong Y, Ma Z, Ren J, Cao Y, Li M, Liu B.
europepmc   +1 more source

Exploiting instruction-level parallelism for memory system performance

, 2000
Vijay S. Pai, Sarita V. Adve
openalex   +1 more source

Simplified ABO-OGS orientation improves training of orthodontic bracket positioning for undergraduate dental students. [PDF]

BMC Med Educ
Liu J, Zou Y, Huang J, Chen Z, Hu J, Xu L, Su J.   +6 more
europepmc   +1 more source

Duper scalar processor : the hardware approach to instruction level parallelism

, 2007
Intekhab Sadekin
openalex   +1 more source

Enhancing English reading motivation and performance via the ARCS model: an empirical study using the ARCS motivation scale. [PDF]

Front Psychol
Wang Z, Lu J, Yu S.
europepmc   +1 more source