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Exploiting instruction-level parallelism
ACM SIGMICRO Newsletter, 1992The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented.
P. Lenir +2 more
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Compilers for instruction-level parallelism
Computer, 1997Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance. What technical challenges must compiler writers meet to better use ILP? Instruction level parallelism allows a sequence of instructions derived from a sequential program to be parallelized for execution on multiple pipelined ...
M. Schlansker +5 more
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Scalable Instruction-Level Parallelism
2004This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for out-of-order instruction issue; it defines the model and explores implementations issues.
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Instruction level test for parallel multipliers
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test ...
null Ma Lin, null Gao Yan
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Instruction-level parallelism for reconfigurable computing
1998Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural
Timothy J. Callahan, John Wawrzynek
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Parallel Computer Architecture and Instruction-Level Parallelism
2002Welcome to this topic of the Euro-Par conference held this year in picturesque Paderborn, Germany. I was extremely honored to serve as the global chair for these sessions on Parallel Computer Architecture and Instruction-Level Parallelism and I look forward to meeting all practitioners of the field, researchers, and students at the conference.
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A combinatorial architecture for instruction-level parallelism
Microprocessors and Microsystems, 1998Abstract The work presents a new principle for microprocessor design based on a pairwise-balanced combinatorial arrangement of processing and memory elements. The proposed apparatus uses two operand instructions so that a set of executable machine instructions is partitioned by these address pairs.
E. Berkovich, S. Berkovich
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Modeling Instruction-Level Parallelism for WCET Evaluation
12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), 2006The estimation of the Worst-Case Execution Time of hard real-time applications becomes very hard as more and more complex processors are used in realtime systems. In modern architectures, estimating the execution time of a single basic block is not trivial due to possible timing anomalies linked to out-of-order execution.
J. Barre +3 more
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An architecture for high instruction level parallelism
Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences, 2002High instruction level parallelism (ILP) can only be achieved when data flow and control flow constraints have been removed or reduced. Data flow constraints, not inherent in the original code, arise from lack of sufficient resources for initiation and execution of multiple instructions concurrently.
S. Arya, H. Sachs, S. Duvvuru
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Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism
2004Parallel architecture design and ILP architectures are important topics at the core of every parallel system, affecting the total system performance in fundamental ways. Instruction-Level Parallelism has for decades represented a foremost performance booster of leading edge computing systems.
Kemal Ebcioglu +3 more
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