Optimization of Digital Signal Transformation Functions in Multicluster VLIW DSP [PDF]
Jisuanji gongcheng, 2016 According to the characteristics of BWDSP100 processor’s architecture,this paper presents several practical ways to improve the performance of digital signal transformation functions in Digital Signal Processor(DSP) function library,including using ...
ZHEN Yang,GU Naijie,YE Hong
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Realization and Application of Shenwei Simultaneous Multithreading Functional Simulator [PDF]
Jisuanji gongcheng, 2016 imultaneous Multithreading(SMT) allows irrelevant instructions execute synchronously from multiple threads.It achieves the combination of Thread-level Parallelism(TLP) and Instruction-level Parallelism(ILP),enhances the performance of processor further ...
CHEN Weijian,GUO Yong,YIN Fei
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A Single Instruction Multiple Data Vectorization Reduction Method [PDF]
Jisuanji gongcheng, 2017 Single Instruction Multiple Data(SIMD) aims at exploiting the data-level parallelism of multimedia and scientific calculation.The true dependence caused by reduction operation hinders exploring data-level parallelism.But different architecture and ...
HAN Lin,GAO Wei,WANG Dong,WANG Pengxiang,LI Yingying
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Design of Deep Learning VLIW Processor for Image Recognition
Xibei Gongye Daxue Xuebao, 2020 In order to adapt the application demands of high resolution images recognition and efficient processing of localization in aviation and aerospace fields, and to solve the problem of insufficient parallelism in existing researches, an extensible ...
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An astute LVQ approach using neural network for the prediction of conditional branches in pipeline processor [PDF]
EAI Endorsed Transactions on Scalable Information Systems, 2021 Nowadays, microprocessors use the deep pipeline to execute multiple instructions per cycle. The frequency and behavior of conditional instructions mainly affect the performance of instruction-level parallelism.
Sweety Nain, Prachi Chaudhary
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Instruction scheduling for instruction level parallel processors [PDF]
Proceedings of the IEEE, 2001 Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures.
P. Faraboschi, J.A. Fisher, C. Young
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LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs
IEEE Access, 2023 In recent years, virtual reality technology has become the dominant means of human-computer interaction, with computer graphics rendering technology being a crucial component in realizing virtual reality experiences.
Peng Wang, Zhi-Bin Yu
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Automatically Extracting GPU Instruction-Level Parallelism
, 2014 James A. Jablin
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Optimized Realization of Sobel Edge Detection Algorithm for FT-M7002 [PDF]
Jisuanji gongcheng, 2022 Edge detection is a robust image analysis method used in image processing and computer vision.The Sobel operator is widely used in edge detection and image processing.With the development of domestic FT series high-performance Digital Signal Processors ...
FAN Mingliang, GUO Zihan, CHAI Xiaonan, SHANG Jiandong
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Instruction-Level Parallelism and Parallelizing Compilation (Dagstuhl Seminar 99161)
, 1999 D. K. Arvind +4 more
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