Results 21 to 30 of about 45,362 (262)
Design of Deep Learning VLIW Processor for Image Recognition
Xibei Gongye Daxue Xuebao, 2020 In order to adapt the application demands of high resolution images recognition and efficient processing of localization in aviation and aerospace fields, and to solve the problem of insufficient parallelism in existing researches, an extensible ...
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Optimized Realization of Sobel Edge Detection Algorithm for FT-M7002 [PDF]
Jisuanji gongcheng, 2022 Edge detection is a robust image analysis method used in image processing and computer vision.The Sobel operator is widely used in edge detection and image processing.With the development of domestic FT series high-performance Digital Signal Processors ...
FAN Mingliang, GUO Zihan, CHAI Xiaonan, SHANG Jiandong
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LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs
IEEE Access, 2023 In recent years, virtual reality technology has become the dominant means of human-computer interaction, with computer graphics rendering technology being a crucial component in realizing virtual reality experiences.
Peng Wang, Zhi-Bin Yu
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Evaluation Method Based on FPGA Emulation for Resistive Neural Network Accelerators [PDF]
Jisuanji gongcheng, 2021 The Processing-in-Memory(PIM) neural network accelerators based on resistive devices require careful simulation and evaluation during the early stage of architecture design, which ensures the accuracy of neural networks to meet the requirements of design.
SHI Yongquan, JING Naifeng
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Instruction scheduling for instruction level parallel processors [PDF]
Proceedings of the IEEE, 2001 Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures.
Cliff Young +2 more
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A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture
IEEE Access, 2021 The technology advances of CPU (Central Processing Unit) architecture alternate between generalization and specialization. In the past decade, the general performance has been enhanced while addressing the new brick walls that include power, memory, and ...
Riadh Ben Abdelhamid +2 more
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Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization
IEEE Access, 2020 Evolution of semiconductor manufacturing technology leads to the rising trend of leakage current and the end of Dennard scaling. At the dark silicon era, aggressive power gating scheme with quantitative management on power-gated hardware resources is ...
Yung-Cheng Ma
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Efficient resources assignment schemes for clustered multithreaded processors [PDF]
, 2008 New feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate conventional monolithic processor ...
Fernando, Latorre +2 more
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Exploring Various Levels of Parallelism in High-Performance CRC Algorithms
IEEE Access, 2019 Modern processors have increased the capabilities of instruction-level parallelism (ILP) and thread-level parallelism (TLP). These resources, however, typically exhibit poor utilization on conventional cyclic redundancy check (CRC) algorithms.
Mucong Chi, Dazhong He, Jun Liu
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Loop pipelining with resource and timing constraints [PDF]
, 1996 Developing efficient programs for many of the current parallel computers is not easy due to the architectural complexity of those machines. The wide variety of machine organizations often makes it more difficult to port an existing program than to ...
Sánchez Carracedo, Fermín
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